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# 5942 entry level English-speaking jobs in the Netherlands

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[### FPGA Team Lead](/clickout_alt/4aebacdb20024399?ql=q&sig=241a0d25424dc8b972e1b3625ff772fc2537e899&e=Z0l1-q8oEoaGBUaJEqqGgpFKA4gdjsYL7qw8Htk3nNM6_7jhkCupfvvYj6MyIwxlGNnfso3LokV_mC_ks_v45Ge4Y_ubCedGv5MewTSg3NXk8nHN5Vpj_QusxYg-wvyaPHBXtoF8yGYqrOJymUnNmMiKBXanvES3-T_87FxS5zn725OQGJKCl0tGinepxWRjiC0VK37dtQ7XYCGnEZRzXPNDEue-FfzbrO9_Zus9wGE03Ah7ER-yXpk7AGbxACdWpGUjVqRpgPW3ayJzdC59uhnWLPu1yZhmBFVEBR9PFbgvhTD8TuMB7MVpK0wz3rRbT7GB_1LhUtoY6y-ORnlTIdV6IkWNJXRt7hzK1-vcgadt90s2UpA_4MtxLKR2ju_Zd4dyJzlvDF5jhIUwkt2byrs3Qqdwuh1YSHvKVKPE7Ol4Pq_4rcv4zczW0U5n54VQDa4MMv8hfjaKNvC14FJMA6S1HhcC6Q6Q2ujsVsFkDFmmJe2qCpWyw1yLvrXHgw2vvsNdS2i6MfSg9X16LxjSmgpzn-tL-Pw1zu8OAUsCW61xPn-3DjHqm6WdhvCU0k8nJU9VmQuBIcGDnmps5vdD5ulHolnDZjxu3V0tNJ0ZKOQ0dajk1fsUcbHLvhaazALl84IPafXOBBeYUIPR1q-Uy3f-TjcFDsJ_boYIDitwFX_BM7bPrHtwH-0xf1iIgse6QC8jnJ92ILspRBRV79cuQPuTTQxSQFZQQoZ76nZKaeT8Hwqj16d4RUji4g5C2lwKmvkIIw-qRc5_5NKBxY39Y6PLwuxWSJIa_4uPQg4A5rUAwGSSSlxUWHtgwqjogxdiZGATeSSXWscrRQowSWz2rsLhIc69l65-KedIrsE8PvfpLESZpXWBCieMGZxYlFxO2SVXphEyjHUHEwPLNzZ1CTnKwl-GV5usE_4sCQrhDX-Bmys_IN5-g0u5F1Y6Dydnh8AZtHdJAjAoaUx3GIlin5Qhmyq9MUywl7xnPUSDN3aPUTqYMAqrNwY4V9v9X-OhBEovykZyCWbF6aHmGWY70-LBrIukIQCrNfZM0DoRZ1Qoi4GTWwZ5MErdh_Jh_qzoOhZFtpqiT_jvly00dANN4I02iYbAdOdzbnKHpdYygf5vA9Puv5mvwmFFfkEYi9jpG6AhAl_s7xUuKSy7-zN_kW4ZykQ9GKDoqG9OVwGfcbh4iYjFdHzkLgr-aaw050xZGbs9ep13Oe13TFvF7ERoP0cW9tI5zrXMcg3n_a38FLStQGoHPLkZ97DE--Hh6KnbUjOYHDc0owElkj7HNBZbt9hBFLDQFzrzSzzbM4ROAQBhvjoyzpx_AuFgz_xci8kFdsLZUR96QA9q-A&prev=RQ035BA3C32AF46C&p=1&pg=38)

* Intellectual Capital Resources
* Harderwijk
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

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[### FPGA Team Lead](/clickout_alt/236185d367bbcad0?ql=q&sig=62e4ccd004dfd1f7018aff8b37b0917d1cea64b6&e=8qj-0omNx-r2JGPWQu74ujHr-XLxR9zGysQyLXK1AkAp6cQ-F4khKCpd6G4sKgk7pUYyxrujai6cFbbocJ50l0HouZeelM2hr7sC9I8ygN1-Wh-mq-bKzI7I0Tv6O9AeOKPpHikS3gu822aLgBhz9Nh_azTCxGC6MuqHaLnkCzaCCpdoaXmawLKoxdrI4A1zOLQs2Re41T2-tnF7KTx3SL9r9YqNvTZBr1lBzunXzfWM13dgRZVXnv27hJxQHVDO-AYkRD8FgGMjiR1hMidiN5TQ04wntbwFTaKVSjXVPgDSGvBvKXQyUmwsgNhblmTH0beX7vYVlNCs9iI_r-9j_BS7OvQxGB0I_w8jRqnM1UXaHDku7H5Xf_nM802RDtgiLZN0sQu8Tz8PwI0TDCbEzYAhl4mQKZZJKn_jVyRNJDpEoQx1_x4nRkBFfEDXWY5AKRvg_Iz7jHZYYLByWhv4ZVMAwwtAead7zlq3DrchIRxRTdkLgdPhSMS_L4W55LJ60My4_TlIW-ol3DXoVItbrBUHjO01Wo1jpcoWM451A0cnvNUIqBo27CqVlBg8k38Ot9J03Fr3AxKtItgpXg0CWpn335cIK6-IY0ujzWWWnZ8YnThQP41eKdYxOz0ERN2KA4yjLTgfMIjBM4FUH03YQEdfpR00JlZrbwPAqAoCeF84y91D8Hj6cXsZSTVdLqEMUNw2TS3s5GB10qbtfRWRqvgt_A-PP8HW0PdPqPR3SoGbTpi0s02-pgRPnZMqH2SZYnQ0pUJkMxJa4wlCX6KNNy0Eal0W6GNOzPPZKFLFVTAiGIfKPVJjexmQeUS2-pw0I98RwwCNXbH3i1SALMI-sUuenR-om6_L3AAAUJDrXfaAreaTKummQ6lOij0wPj3zJSR2a3j4jPg4XY7Clofjt5_np9QddmFvdm6EKf6GKDxJezbhwzRUAYyBWtDYmLBsPzhF6lAza0iE90509EWjnOyItdp5Pl8Hd8qdb4ADUmoVJJnXd3aus97mKQFYBcSUarKuHxsk3iNmA5dy5hhO-yPVQ0i__vlT1LDOiq7gbyO02xbn0Smbu1tEbsF4-wVJWCCay44tTrQ3W2U8tJ2Gs1sKKmun3x-2Sfjt7vWsBuheKYTpowCFgrrPJe4X-6IzAnv0gQlYDU45lm5tVZKrSdRi3O9HwbAcaHWZ9phJytuwifA2CqNvaTcimyAYwfs-214e0hiC66V96SePvwj3CSv7rBllk60kWou3gvdk7h7AFIYZdKqJ7o8ehmsfyk-ZUuBg_9HqH_wJ-evvbcDfi5h5O4vwphUKJCWlx6Q_rZwRT9OBl53Bdqih5xdGqy1qK-0M_WKE8wE&prev=RQ035BA3C32AF46C&p=2&pg=38)

* Intellectual Capital Resources
* Veenendaal
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/13362b6baf3301c7?ql=q&sig=3e072d55169ab9bda4d7e4806c5462d09b05210f&e=FYzHIM8c_oNqyTedcDiVGvuiCJ6ELI6R6qU6LJ6iuMMxCJPW22ZlZhrtj_RsLc0lFz6MIE9pQHeMNuu-mlfOuSQ-wI4o-szbL856nmUlWGeMQaJkp4qL9bjc3_rDm1rj0aUfejUaVBdGMinEroFDRSQR5jjDIpXgM1Fxirx6BMXFBws6D8JMu8Jkq_eRNNqyr2ifJS1fu9XX1dZbyQvqv18XAI0cfwfD2q1AN0YMRNQOmgt6-e7-Y6pu2DPRCItSqtURVjYt_BZJyahPdC6-l9GHnyZmqQ1rtCylzJwjQJa-ImzHAbGEISW8cMHF3JOmKurEKL-FRLCrHK9u56ACxKgbsCFw3fVpnCjTbXWgc4tH4zRGf8tPkWVA-rHTBKBZzXMuvLpj4ElOu2KqnvCOrJPr7jBV30OjSEiLFdC2ZCnkZ16flrOlYJBaM1cS_m_wiQ6PeZtXAQdrVJDYuf1tmVwWNyCcdpwiIELb7MuPU-mYeQxEhDESZNVy85eJs30DNCzcarUF62hR2w-mj9Bx1V4qIx81FggVli_hpkxeY3geJfNHZSvEDDVnNqMWl6Y6RtEOAXzIbFvp8056HBLgesjUhn4HHyzm_5yiwqBjbcTjtHri3yVzDxN7msVu7_i2G5W7vpj-urbnr9PZSI8OZ1Gv69WxiGKvI19VDNshywsFrExFMJYWWIVQWbdBxRXd4OjSltZI8zQqBAv2UKSdhAl3N67uUEywxLr9PkU7x-zWA6JZLMSvMWmzoRACJYyUS5PpwMNE6VxNGJQSW2CEbgsT-7qwspj-M132tZzwJujV4K0DnYe1nzMQWOocKuYD8cvF_SAjPeMwKQ7EIP7hm5bdsMYpHgaNygeG-huQ3kmZqR_fZd9Xdj35s0FhuDB03HQsaTNg7y0tgQM74hhUJG-0VTOPpgL7pAThhjfwYkeV8rnIm6ZkBUwOWE0_USNSyd0Z24UsF9LOsts7XlSyQXW5tsVOEiZ2f1bJr_Gw0SriK2NtM9kZQJ0KC73N-oGXOGYD0AF2TnD313OhokIUIWqSprjkFZMBC1Mhi77ruZDJ8mAGU3Q35GxTNNurloRqzGfJLqYO9KRzWfhSu5RS9UWyOLWvzxTdn0wugKIXXIS1lCE0mKalRCOwR59b2CxeWXFLggCD9javdL4EJ9wH9KSnfHTfN4yq4BV8iFitKITowGg-PtKg8sgFQ1LIb1QB2lzavEgpUkQEqNB4USzuVGMZNbjgxsxipPDWaY2qyduIzfyS94TQxuVRnWfGvB-pJkQJhB1C7K4m4Iml6j7zw1HxRQ63_mtKuqYFEuu4AewLtuMi_peESbG2dk-0U1VC03OH8htiu6U&prev=RQ035BA3C32AF46C&p=3&pg=38)

* Intellectual Capital Resources
* Helmond
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/7faff715d3db3ad0?ql=q&sig=cad4e79941294d3565f25808daf94eedf7515d8e&e=nb5hdlB_a_X3bNZj_KrL8uIz4sl745_Jcma0nop4P7CHeJXsPzaAS8gzy0TYgxbuzdenT2qwLkKVOKfMx7RcyaupS0lK9UjNGx_kwL6wwxdDswsVnxczvWzplDEN_be79bbAWGufNFYfcNjl7PH2OKnc987vLRfc7ZdOeZeqTBpOjKpdqfNy-WQRSW1JkWR_SoCz_I4z8HzFKjJ7MLlwG9ZyCHJLNw5TiYg5F_RYSGyXJwF3M9ruZG4TrFyvItayXdk74JQy2sJoow9FiGmuib89pFuvItsE5R4wY1hG0aTGQI6rYU6kObbBkGE_OJoaAlu7J8mMvzmuzQ7dNfEoM2qLu6D-TlSSA-j8AAPtId6TtKfwQJggIPgkvuvrCljIm7HiKyDWFCwbiWPU9F8MSVYcbuT84hyIyOVaEieJeZ9NovJjbEVATdAZ_R3_aLKrj5ycgYQgByVlJrRjKDPhUpODwLmRUK2JriyxfkMhJsw0iNSzNAFbAqz1NCuB7dpVCDGjV3iyle6CqNwAC9hE4F4u6tskUtYrsSVYO_T_gYTYxpbLwa81EqmeJRxkqB05QSUV9SMhqTKVi4f_i6ONmBhJQw7aJ_FyJcXEgltHODF_pvXxAjp-pSjlGFmAJsVxwTJvite_NI3hdySIxLY9YGFALpp83SzfuHCYN5UgfyiLldikGQPscxfUe5rb_Z2RQ8MQDEa5_iwv8E7h3CGV8YgElgb_9OGEdkio7pbo3s438SICZ_gC5wh6nUbwPy_PCqwro2GAxoxU-ughtHiP_M2DPIniGTkdIK5fMH9hc44KTT5dtWc5-ODwnha-JtLrsPjd719pbeq2_Kze5kILaxYfwf4H6SI044Gih8gI0APeLhtrBQtMy9rINyWj4VvWUuaUwgOfFrCH9P3TY0i7oE25Ic19hACY-eoyo3pICRRfN1ddN-UF9gjAbBJnUq5EVZJADmrG89fuHGOo01siU5mIIBLTOpq0JdX-YxRQ4KDpd-pfG43UZMvaYeRZixbqiNvz0TUXCNBdcfx6Ly_c22r7hxfPq3BcWcjIc5VRM0JJV5Bp-uH9dq0aQsrWZKEdWDm5Ued5tlCUHSUCkGT3k3u4lQfb7YEBZ2NJF5bchMJxqXF_GWordTHN4hQ48zG930hvtUiVknlP9ggPbJCGBK-h0SIIkIOB25S2oKqUUl_EO_W6hVLr02P5AsS0CF8ZdzyHhgjyfay-NotAlWfon76WnIQvcLCIe_LzKwv1Brh6f2VlXgXoP1KXadlgo6hTug1XdX8-zlB01HuOq3mc0a30MX81XBY41mfVPetI0TMK2giY3HJ54I1yWpyonkveaVsJWpyGrx3FaA&prev=RQ035BA3C32AF46C&p=4&pg=38)

* Intellectual Capital Resources
* Zoetermeer
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/066213a6de212136?ql=q&sig=14e5d52e66cfcb97adba3b956e635fe40241b36d&e=KJaJ3UBXdEABjPGXhJcfRtMJIk4fj1mSS7fDVcnVkVdDB2X-L4_HHFe1ofoZw1Z-9WCvjxUdrf4Fn8x4uyYvdXpYIzDygqU4OmdnuyBE1gXKjr2KgGSbTC4UgK4OHUSgQ2aVcPU3R_XESl65kgCzpAZZEIfP0gaVmo64miHxBQyxU8sfOnCIAtj2NPqeFPLA_ChdWnf6qGb1XCgjiiBLnM66wXFUfvD1VMAJcfh6AIDEolNSVjhjLi5uCjpzO2tlmeLR07fVg0JYI1qc68Ne8SVRl1aWWKJlXNciHG8asJ8GcGUrf_dE2-bYDT2cJv2JPn61jGCOlDkhQcnUCHEm-d10HDrkCp5jHc_gD8WDr6W3o91P5kPh0FlfKPyaTFjF28Ybu7sFj-o-TksfJoBenFmuZbx1TDtk2E_bVYvFPaMzejasvDPjOwLB64-VjzAPmRt_4TVcoGcIV2eXVimyUDolRXpGwBh-7ezKadWRVIYNfgj1VBWZWiphdkn6X89fTEE3qV_GGm7FAAl7u-0E8sNBcDP83T3lKxLv7WUN8yE5S3fD192LZfWhf8oAZJ12-xDkaILRUhD4jfJASSqyIKc4HnVlEM1PjDYxv4iUBVhkDhEMme3lLXJ_gi23q3lLy9bEAmvIW4dEsXbagkBzuVFarMUxMKXpjUc3ANxuO3cIRX9fjMmDhRt02C2p-FN-JNaV9xtcH7JYOChuQg7iSvmIuWzDS8bNjB0s921uSWjw243souXo1ew1tm_ZYnyJiikhCM8fz4F6FXaqo51T3xUtyswYFu88WHGxoew8X0jqhqjtuhYxMbZBjwNWUR2VOW4JO-0ihqJF4xy6p4A5ItTEnYpc3Ph0xtTnJmzzr-KzT2bsTRMKgBWC8yVaO6jM7moO9juetFS3UivIQD-r4214cTV8iTykHzFmku18-FJ8OLnPqmanYbLBQ9Iys4apTKw-kmBu3PJV4BuJ4fOxnKHTaZIwtIjLrWTcUBVbhOXZ87rjWxwkOcDKEukQBA2pgYb0i5davBjEzuKy7FHBUaXH3Y1plYvtgThUqHeVOCWrdrCG3cLgfqblxO8aSMeLLxJaYcpGhB1I6zLy5M9JwGIU8R9mvNqwAu6f61x_oEyt75L9fp0g_c7GsB2QUQfcsOa8pRX6jw1F1sbX9MawKprPHv-YMvOCQKYAQo3YbhkPi9zSXz_KqMDMNnRD_qBor6qJ3eWi__uNx_54BrUfqMD8F9dkp27dte605oW1kUJbyDNG5zgTuc97ubpfuwSKmlGoMP6v9xmFpp5WvcgNCEyRSENe3y_Lo9ReqzYv-tASyFShcclmGwE_P5E0QuRdAALt_MqstF0&prev=RQ035BA3C32AF46C&p=5&pg=38)

* Intellectual Capital Resources
* Oss
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/31a73b4b2423b1d7?ql=q&sig=354efcbf402842dc015142d9d234a9a14dfe9e84&e=dkH1-jPhgCeg_Jp10uOBCQ1afW41xz4FrPlridByIpEdsp-_hch7_Tp77YR8yvXD96veZqW_dHLnVy23b3bHkvPn9GO_YruOo4bS50ZGeBX3GEn3D7K5S3symGesm5f7aZtacIdBkVRchsaPxE3t8kCVqaOFx_SfSdJenUy4cOUWE_zA07svxsFF9UawxcFs_HyeM68mk3s-9Hp31ZREM0BiG9_xPcoQy_mfVETEKDKVus0xm3wIcASXQFTR3OpatngtQGUusNTaNMklZ3xI3jxaBKneD6g0aGzUW86EwrSj8Xu2Ft9jAgk63c1E9549mWKm81npwgVpSHbf00qvKvay6PJYz1F77gd9lu-EV3XumImbPc-pj2Ahi0k5sO3lvT-GULodIY1TZy8EFFQMIAgHtwTGNKNM3bXK6WSqlmOc_OcvHvIaOsafYMAr1q1Y6cyKqAvZWaK3W07f1Lvx-_lSdxLI83_oGhUHjnYEPZOLAsdqj_u89SeMqClUiSYLHnxuz4A-hEvYhKESPJWPtiv2alH8zsCwXhuN0bM_ti_kKaXF00OyOoyNn5DPqprRW4jAEdBd0fMGlaGGTsgYnwr1ACKAigczOFFj99XCZT4t69IvP_BHYuQ9_osind81z4Hb9fkYOp9U3Ws7u5-5-R_sDQfoK5t-X1s3cyMoB7QM4NcVJOekqVeA8KjxrkkvDTn_gFachSESifam5FSchVLsntWKgQ2hjhiLipw8uWdIQngv_xqr4ChQ-RtWzfNhrDMV2UP5N_ZmpVSh4lgUVJiZM5DExIkFxuRJBrZ_SMPSUgG7RZpYqSsYfG5yRc7sBVTctCWT2kbWFC0a92y_56q0jOKjtqAvgh4k6cW8mxrlfBPfFePaKKZO-IPZWAALnDseZz8Q3WRjftie6qAUY67DvYrBHwpG3s2N8SxW61T7_LdBjEalEdgje7AQDHOyu1Y9BUTk2RsRDHCF6JbctGYCNcdZFGwE6Vtw5leqEzHEYzBdGG5svsERvjDDdUR1ou25t9k2g29CSwcPiWgONBTi2C0t_KOYZq-1YxzXKEQKtPcjW15LIokeZqImv4q4qjtmIcwWvnC_rZHtqQvyWkbeEAql3HWVrIS-SqHt60HZ7aiYKxG0DMLbxcl3rtxL8uuAxIxj1hlIEvo7-FlqaNyB8wVtSdvsXuxdhrnkImuQMLdhZfvh1Sw7UQchr4mUSZoRf4IDR7AlxjbaPufq9ykdG2dJFuJ1KR9iBiqpb69DQgdLmOC1JjlVsQCuWr8JSWN8EyIg3QZ8pM0qrDUUoE7V3Ng6hFEW3ym59e4eNDYLS-UgyISqGm99T_bhsrc9SrXE-AhJfpg&prev=RQ035BA3C32AF46C&p=6&pg=38)

* Intellectual Capital Resources
* Gorinchem
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/4780a0e32c1f7f8a?ql=q&sig=085bcfaa7f0362851171fcdfc68ae0676570fb2e&e=YL305L4_gjQ2qFri0yUgIqXQDqlW2riKB1uinIiUlUZgxeNgY-_vBbdWXxjQba9X5knkkFdDtATBxWrT1ESB6tE29_afAEg9PqXoyCE94nYz26n1bAfHYXYh0gJstrhm3oUaMjUGfwKhWxOFXaFTOLD-P3pb5Jr9nU6zcoCuyAi_XCGSl77EatVLOr1sIaZg82p2sCzGIF-yB7lMAgrnfhHmQuFFiuDWSoOYpspMBhQcq8U7JrpN_8T_7o_PKCeQURGaxMQvn-nV98CriuBCX0PST0_zMDcCwBWyeu_UkXn0vBvX5wGmTax59LIf3VCcyKKQL_pLl7tADlQf9GQ75-y0kTG3seQdH18qXJNe-b3xjNL7mYPHx6UZlq7TqQPzyfkjTio4WywmuvKDwKeSyUdv8jtkh5KmyHBc4y1Aqf0a2KfGj8Zx6S-y6hPasgQ2BCxlMlsfTzH5JAamB39UXN2SWGZfDNRKeuAtiqwRtYZtAU12FtYSBxZUWmNZdcUx6MxDYNeu9Wt5OO1ep3bMOHYBFqAWpzFMGC-QjyeU_PqDLwHSXqTqaV3xrJSFHajfJ0YUAOyjqcJOhEVMBgcakzNBIPcxokt-tdOHxwDzrejUp9_Meo2MFqQAPi2sL5aCUsGl7w6LUFOa7N44KLeEJTolltYRwk4ODSf-rojFKhV9Y7VS5680SDCp9GjTZwxLqvIKLoEXBfHrdlb-SuuzEuXP9rZMO--auVoqk1NoFga7Go6hV3RRiIDQOptY732N0eypSKV8RQASO4h3gbN5CExBdFEbP2LainzvSLekIPOdteCjiPOD7GaYKu9suZzfU7dRDpFzYG-DKPKP00lSHfU1CViGo5FRrK77fgOe_OtLUKWXFnHlDqDxLDFtGwlN6aqwnHq7yG66_AYp8hQntYa4bXlZ0CdsFHlpe2iuUgBRDoHjTD55uVipJTZNZ3T1a7vM6ASb10WvMTBx-fpwBDVgEI4SeLYv0FHgm_yQzXp-UCk5c-Lp9S-1ohs_SbTQjBET4tew9-E00wEMExPb_DwqpYqtWZgZWgbElHDoZ27u3wITizYsWaiQAZYrW6WniB4NUo3ItwRBQakvWjbMATCIP7xyl7jILAtfQvI7VbdewKNVX8-4voVY08HE1O54MyjA2c8_JHGZWPLrFcb1fiPVF0feR7dCI6z1UTl1sx5hf68xK7cQAXeo2klWn8Tq5k3Yu0nbkMXe-J0VYPIRa7W8zhakIstNC6ynLErg3hhq0ADEkilI0iC6ebdvpdGUx_AbQW0dAqGO0DXK7Xz7AnEo_VrKCWu6WS8ShWMYvEUU1XMklK7b-U9E39HtIjqTwIYvghLww1o&prev=RQ035BA3C32AF46C&p=7&pg=38)

* Intellectual Capital Resources
* Gouda
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/06e52f988d2f892b?ql=q&sig=3f4521edfee292feba76490aacf79a307a695aaa&e=4Yy4YWKihB0oDw0FdsyX2grmIpmfbeCQVpRUJeDZdw8OIjO93yB3TDC1l-YOh5hM3-ZKqGGRqrIiOi9DHpnLTi9H7bhPGaxi-EGTVo90hB7IbahaIykazugL-bVFMkneneTba_FAsJgdDRX6YnO_21BkY8u9UYoYDn94HnYEAPFrv46gecfx4L9sOg_Sx0sjIh2Z2QsBkk76tZznL1RhNkUCxnKGk32h49ODA5nr9kyptfviQMvKcmxIuSDe4z9Ltx5ongQT6FSyrOs6D4ur479WKWbksOPkZVmdsirYBYrRUXLD9kIsjwWB7Axr85euRuEuBsXIEyba7PhTZAriUG5CgdBVezo26C0EBZK4CeEe6RWRkEbmLfuW-cgrTv4Hd5qcyM49C8lQ6dvYXZkDzQBAO16uNTHUrMtHZwxeOOOzAYg5sYj1nKkWskSXf_jzzMK4kyMmWhY9mLtM5EFLVSO6mSzs0Cc8n0oMqrealCpJm6Ik5hiUaDvtAXCHmv03OGJfT-4X6pLfrxBjYG5FUflS4jLx-shhkr7ISOJl6WyvqxThhbFmoqRQRR5Tc6MJNVr1szWxv4MtOf_CKQqgyJKTWSgMXnvv2PWDsR6sGAKaFtR_3k8QHMSdlrJfOzHf85Lc40UX3NlFz5KdwrNyfbWnYE3q9PVcIYKzF8lSfNoc9Su_XVSoikve0TcIaYNL1A6ZVy85KpEDz5iyCTQvcyOScb3z25PAsMnRnRfqOCgXhsTeDVVy608-BZLKF4xfyH3Refg4zajl3FVHcVYQdew333TNcHFGli783VtTELz4lY6bIMKOGlKS8LWH04HkdGYV5gs1ANNGthE7OOd4WpyqSitKZPhOxULKAJ_kffXcuIvmsbo6IEEHp5cN2cUdM1gZXwMwV8g3010Hi75v2fMqXQq92zjNSC7jXfQcEB8rIjv4dZOREm1BygFnYOndwXC683sAX5fpA-Cv-ZxJ4tg9NIYPkoscFltkkZJx-cEzixxRlJlMV--CQseAHVXYmHS0C-BdYbGyCsfb7hOSHdcFrqyn3_mUGV9l7_qyb-N4OfjLlp-Jp_qzYUz70tRgm_F31IBmGGwsLEk4oQW-xK0XClwf7g--Lfo859Bed6DaGSAPJ35eIj8lUP-nyshML1sEQA3k5EuIunAQ5FYSKMHJ7ydUaAGWWOjwG9PYfua_mSfv_b9xHWkDi3pZqRZwQHryfy2dmRIpBA9-fmm1O4StIOgxZwyKv0LKFFGlnTtUM6aE3OaCFLikq6ZfcEMf3Tz8XcPNPnb9lo9zoMFkSsH2pcoLTvjJUEbNoXvW9SI_UPieUsv1wC-x_NTgAq4eejYvuHC6A9jU&prev=RQ035BA3C32AF46C&p=8&pg=38)

* Intellectual Capital Resources
* Leeuwarden
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/fd070c632bfafa74?ql=q&sig=d297295debc213b46f45069ee794b1f3f3519968&e=Xapjnc-bbIV2t1slwiNzfuARONx2dyCssUO0YcUrNP3JaJNrVvLE8DtgvzZGwe7TBS6Zg2qWGeZQuc7MGY6XQz_gMuR4zPv69hcAQzlybM9ppxgmkoV-E4HwZEFokLuDXwEIZ9SULqc3vO30EaFtVW_IGTImNknsUihpihWfo-aZ8HG8VflSz1_lxR3nf1OVKuQcUsQ-d4iXl5h98_kuBI9jaom8qvEvKkug0pEOZ_A8VSurXxM44u_49WF9zEiM6_AId3Zuj4zcWcVSwwl5g6oGsHEHUz8JFRVLvDj2x-ZNdGst7Usig_dPwudmWRZP7lsZI47pZAg65-lQEG0aK3-NQKiDmNpJbkKxd5duin__ZFpzYhIkzcQ9TVU67J9b1VGA8_0LiIELL5xZ8n1qW9xdZgP-1iOhS5Ya-CUOfdYj_7t5JfAheFGa0cmA-9AutRjrHFN-RjRb3Q7uGTzVsWoTZYdLJN583XZIGprpDWNUIUgJ3AJN75a24H467yr5muYEI_SkVoCwRxhy5Te4BsOeXVb7Qi1nlQTae1rUxRzd4lMAdkALUh2NlpTI3cI56bdgRChB6P_LVOWyGecDPb9od1QIO1fLH3Wlx8b9Ssde7fabFSZp9qV3R013aKhsriUwL7KrO3nIjqqekQ8q5WF9ljlr7KtnJJowDQEcjI0k02RCCGqqib6UoqAlSGnZvLbOVut_gnhjJzQzTH_xSyJQYbmoAapKuhDgIERDdssjOmQu76MgF_iusJY2TV2F5Vu3jMyRNQUwjSIq7V1UxXLsN0F1MFD65-HV0z0Cjp7xLPhIpDJq-AOyllIFFtZCyvAPqY1W0qx6ocYE-nln1N8ETFVy_jhFMm__63BfNy2MzZUGVs9UKUR2nEQV6fERixV4qMIrOgCUrhw07dvDiWqZ6UJ9Vg3Nl4BK8TM8wOe32VTSl1fbYT8y0EZkkSgfk_716abvB_-c4FEcLBVe_HVeTqjMqk4IxoH2qQmIRhK-p9iDH9ZIQCU9J68TDhOXcpWBgIrS7eIXhpqSBQte_HuzP9vrJO521pGJdR4uu2DlzhCYLpiEmthBGT8S0B4IPCfiJo6rFjWPDHROdeU4ZF_2VFnlVOa_F4sYrL5gpQI6Lw-RLW4k78csUVkNDHMrVifN2EXRFWwFk-3ranYp8t8LiFjJ_TXDf3Tq-maIqLq_X-PnD3-b2inYK04UvX9I1pXmHbBTbJSsSbtixja-xPyF6qvn8bpzAdtqC9an0EHa5GthotpvoF-gDLNGYCBFA-CkRZXWojzj2YlPwKw0mplC_LtoQ0T6ZPNyNvWh94iy5dAo4xwsI08dVKRTVzftvHIPA0_0Xik&prev=RQ035BA3C32AF46C&p=9&pg=38)

* Intellectual Capital Resources
* Maastricht
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/fd4d5cf908166b8b?ql=q&sig=2ee5e790aa3246b35d3cce54e9575bdd081279d2&e=unp-5fJ23IKZFY_vCDJPBrFTwKB7hqE2p6bCICOg-Xx5ULtlmTwMUqRB_9A7jYPbWPVPlhegBwjNejQCvxdW8UlA2eo4wth6kk6BWPuxjWFdjQuvEx_ciRatIig8nyisAwjcpoRt1bDzqpf6-u1X1lFauevGVwHVP0Fxz11r4KaPJL80tM0lc-wKTh5k6mM2Mkp8Fo62cno7fj4KjCEV5yVbRBgKFp3klaeZUMv0C8f8ONqbr2TxNKOinepgyH14VsF6qLPeqXwD4EkZ_CVvLT4MEtflwxO8LwQ7dL0lDuTnJwbgTOar9qVu8_fpY8msEWr5U9eGD2QO32KLTRar82ot7YjyVWiKqyMvCg0_Bl4sEMsEI24ZnsNliwTMVJCPbZXdOyrXTfai64qjmQsjsXr4-BJoQYe3bNFpePU_b6JmEhOzhYdvSDGmRuIH7cO-ekOu6kPDNzXZsn-NA-ukvJmERsapzu1XjFrV4si8v43vnnfo2w1WEqn4QIxfgZnKpgMMEoNSH0t1gmcGhg_5dGQOpQEaH49wIDcnbRFZqvp9hGeVSSwiuLpYFazn0kd9IWPe0eoWZ2DqCHDo4JM3jyRwLqep0zC1EMDGL9G4qYmO9sxrTaabr0t_w2LUDxKVFORkhSvfr7fhkRVOsORXUZF0WAgDEDmqPacnjYhBji6x2_xYl4jwLhZFUskHjvMp2Bn2og4g0s5gmvTgRXM88xZBtee7UCtguoWPWaqB4nJR-dvjwir-NOWPK4EMtXdVo6Ydt9yQp4UKWdjDg3AWt25VqogNSMWzVhgdc74J1kzrnrwaSRZuMrKO69RUNw2Qv7nYVcBEM5JlGrS-TrWDyQsKKj6V5AghWUlmpwLY8dso4ua575tD3BLVKGwVJulh8KfWfyzdajS0uzN680L9sGAaM4I3xXK-iK4YgqbQVkNNGvRFuGBbGqo3GCr9kQNBOqUHd2qTsPMy2Fwh-Qen0pyiip8eXvbFyOCM-4Jb40uEQR7VBzZW2lpavdZJSvJx0q0UrGcLS1a0m9WjHEGNcObNyKSt9wYuPR1EKgVv0Ywt1HC6-5KzFJgXyg5Sgr_Nhx8kmy-DDQ3elckB6fstfMc1b8_WhaYwyM13SzIZBayS5pcs5LwVezn5KKNBJxBO14r0x9iymPZqCowXUmpIhY1Td6rtyW8IqhvppBpllw6IAijuEUWm4hOO2S532S5nzYcTO3t8oRLkhLuV_G7sCEwwmWCDLYx5epXabKyIPZ8Ck_alRtLVYbP7eTy5rWXWkkPPb52tE3f-Ox2GGhWmpFAK68V1QPWNUyuBcWGWvOaRqMGRH9JQKk8EifvvxygoHtbqqwUzSCkckpuc&prev=RQ035BA3C32AF46C&p=10&pg=38)

* Intellectual Capital Resources
* Hengelo
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/b388f5b0848caaf3?ql=q&sig=4c6437149e92fd6c0c6f7775688c044018c660c4&e=54lYWIkRalW04jAwQ8SZcb7eq8UDASpQkqsb2e5SFdaAbDxDlGMKf9fCb_c2cTP_C3hEsOKAKfRMJjReipH_ocyWjc-a0wy_coNmMV__NfcD3_-R35_xwr0EsWbNXuIb6XqRgmrqabQF8Ss02ZmlX64abMNXoQQgt0v0onL5wplNhdGOMdZTflDfxoFN9YZsIOAPDDJD-Ee2E_XhFSlN15-HffyOKUnSCfH0B1IqCnNq0cGvLoVhata2R68n-buC-2DQzZ_mnPRa7Q1RyjTBFJvZo5QKyg49x7FUu8sKl5awP19-fXbWBYqzaFj0S7Gwl2-RXiPC0XQbm6kRenQz6yiCnjtpF0rlZyHn3XZxJe6ZbQdhHRa98GdpE0MfUqu05trTkT83lvtkB2Oi89OsSnfQjiISu8hTG23ctx_e8XECGHk7_xtuPzbseMktrC0-TCz9xIhQAPs4-fooA8jpH2PvCwp66MzPPli4XyziYj8oceJcSTsLXhJ27uEssG9vcLvrvJUjICjZqbIaauo6UnUYqft4CJe5XX8BAcMHnDvM-FVlM9qOZMpwy2CTHgIw9det6bl8jdgjfL6ZW8Xfnrl6Z1OhP0Ky8jqAVILfqLNQPuZoGZi0shEdiV-a0olWVhlgjtnuuVjFt1Hx4jDsUzCVj4d6Ms7vMEPRPhBW0tXm_KDfjYU3aCKg9-PEwXslBz09RCwnlXecE9baJAm2_vuo2hP73c3E-8_hewn-UKnWiPDTluC38HrMYlD4zJIH25bBJAjAe8db5QaRmSh9N2ZvQw7bpiknk_GDD0AsXXu0t4NKXicRfmy1Vq3bucdZ3wrBWspC-pwc3mscWW4Hhy7OJjvLqYFtr1cV_zQ5ZxiSuWUmIFpkK-sMJQeGBfrKI1saLZjlQCIpiWajVChjs1roBJJvd8__-j79pmYymVfZnTuZM4DHlwpPOTnumdTZQsUoDyFai_tnjo9n-DZN0h_5Q5Ao813f_7Mm6frmdelbq3rcF1k08RqzoxF5Tzn502VCgyvekDa0lt6BdG91iZu2NIKsJHJRcoZYiijmq8231chtpEkXYs4XzUCRCpkenuvg-S9m80rxGeNlrIlebgi41UUPdn_u67UnOhmDZVHUqPq1jn_cMmXBFs6M_gbRFe-gDjlgQughamdYdaWSt5cWXfLtCFFKKhlHc1ongki-DEiu-U1eMjIEH66YdERC8Eh4oJMetcBsx87DMgqAnsvfN9vqCUZHA5wuky7gnqS7GX9qVjZKBjQpjGasHpU1OJvyErHvcUAgeaFKBvXL-6_CujdjBZGtEg7DunZRZKAZb84Jwm_VHIScQS3AvyC93UIDEbEIimNtjQ&prev=RQ035BA3C32AF46C&p=11&pg=38)

* Intellectual Capital Resources
* Almelo
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/6afd3b6d096c83ec?ql=q&sig=6ea703a45dfb127fd53275fcb71f5b32128c00b8&e=1Qnobn-v0mUTNySvv7IcglRZfTO58u_ghKVGHxcPnVkFHUGKe1rhD8y0Fd5lkVZ6mfcM3iexZrLQLdO--HozH4Y8Y44GahaAviVItvI1qX-mE7YFDTZe5jODX5DacCGuV19l4I-Ncq_JnLnfesJyyHTDh4XUB5O_KEiMScGNyxWlWgHC15qh4HHohWq0SBf2x9N8aemaBbSa9LF2KKVnMQFnmSevbSdeedbIuMrBlsWT6AtCnBCfYJLM8FjsAYnk7Coq5OexW8P_M3rDJGv21xfXmHTQb41yIliEEhb-jw244Yb-tqZ8RSBeSccNjixqzjH_2p9ZkdoRYp3CyaEfQ1mp-ZzDbe5Meh7-TZCL6yM63Ec3fQIuDAZR7oZEIlhzMvCKyFBkUMuR2axQ-En2NkizGQ4BPpWJ2P1_F-qGED4wPmrtFtHjAUZN8pVdDrLwvuO07CQm0MjgSZKAcCYQF8ZmEH3dwROjy2TutaB9sc2anLK5CHVuqku-JJSdyTUqZhCbu06_pZR89KaIza3dXZM9XPswWtw_LUW1T7xT3FTgq5c58EBdS05TY2KSQzcxJF9DfjS2p0WJ2qISOTVIZ9MGkjd6TRezc5A85_eRE_6PB0WoC4xA-ZOwBb84BxcgPQiiLq4IWXH-xFkTOJqL7d2m40OX7kcXK05egmold5YhM-oE5XV8jDoQdxIRMOWHjoHmXniVpXVGG-DI_p06257ylsp_2SC8cgSN0hudWbmbxMNSc409DPj_rpq12zCla4jvCTJmKmPLg1X-GzzwoQXdo8JWMjfDyL6eznH7e9bHahZ0YGMrxRjob9YewKsc3yCi98vzs6pLOlzRGF3yNc7--5AZu_95Y6upHS5uKP2Uog_cW9M0GcpG_MzFnCaoNJ1DWxkEDN5_jjtExmjmpwXUPvT05G_YHH4baTQOf7FEprI7W7koeIn3u1Vq88ldDrfCYBhkLIZr1C-fnXmCrfDIoth4OGAaTqE8Y9BS29mjB4AHADUTpzGyPyB8KCWGyEOU4-oe496wwSkSMtonSWbsrN9wq7fAJkHZWellUF8ecjN_QdevBmXuVega7vv-XXfsQaKWwjrTM_4K2HEFmGWvi1lqnznppV5Wm49Q-ameTLdPQodf0ewDEP0RI7lLEHSDgAnvRtw2z13M_4Bz7uiSRO9wnoLBMKUrXDljNSScV_cR3H0BxIB7Ja8M2NBxRjXkcBYT9WzVS_rMoZAh36SN6QaD1u0Z6MSiC7V7NIjjBMqmWtvBMEOBBOlV_16d3BxsO8tdI7Dh9NHX49d2chnNqpXU0Dw1bXUhXdtpcreaWel4I8OPU4Bc1VACSFkZpvi1RB5EnfiROQ&prev=RQ035BA3C32AF46C&p=12&pg=38)

* Intellectual Capital Resources
* Roosendaal
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/b7413215aded8da5?ql=q&sig=323152ee8f1aebcc8a5c1c5241880eba548ffc12&e=f4hyDPpKUA6y6ThU3zIvItFITxSusMKrZY8KC0WiAkN16TZWe4PiXq2hQ1QBRYRNJKjJjcZyqmhwvcZS65uWzxe-Iv6aYQurSxIYRGctcImngIuCBAPe6tmm9xBSk_uBSe6tCG71aju8PCIO4smh5NHrOUPZVTdYfNbZQFEcFfreXpjdEeO3tg0nRo_bMG4ILjeancbE7Q8zbj6zUorQxHuua4IOuiDczQ5PJenAYE6GjyGCTJLUKreCoQ_RS9BVGjqTvFszqOaUppCA4LC4rLTXO2hExKHzLSw7TSYZLjj1khcdPfh5uPjfU-6x5eGN5_w5YK8OGBtDPYtMVHGzVeFZEVpadrcm5r5kp5_EjmBGgHt7PLNG7rwU-UkClo4DjzJMuxDC51cSKqEnjJOc-YiienKb3dtFo4lEcX1Jcqqquhwe3ZixtdFg_zVDBgz5x25-bswq4-4zEhpWYBT7YtFa_NtCaSMEwRsAwoD8wQlnANC-mUDl2oFVsOHHntddnAQTWDSK3QxjTOF_n1_oppqwWzk4PGfQGWRvuWwsBZVG3_fMV0abq1Xlg418Fx5ypeEro7fl0GePnybBe2hvoLbhmLwTDuTgfqt0Wb_wsiFY51mFM5WvWxTmBgxuxAkUg_cxkD8mZM1f0qt8UPl5iplPjhNvM38bAFhX4iUIPCnBBEawdsMRbIYHb5T3ErdaUoJbOay2uphWl7gumm3HvhpMzLcWAy1W3-Rierx4qqccyJiBjnMrF4fy8z4BUYNgIGwvE0Vcd2dhpdhtD3NaZDEQazlRRCaFHZiLwOwVQmTE9zbxWNEOzxA1lWf0Hp9R6AecCL5QDk6M34pM2dy7UOXOQP11R-hI0NfdZIwOtRs_LfhPx87uBO-LDbzFtMaXuL-v7hUYpiNR0gDE9GFFjq8WuLXENMeI3qS2mMJTJqGky4L7owKAxq5zIy1z89Mxv_znHk3znuUn04STJ6CUQajQ3phML1vYeCjszzncRWDbCwPxBNPLNJFiybrUMB7CNnfeNpQULspaPd7lwNSn84_OS5pXXLeX33KuRYMz2x4phcmdwTlTHnAA694i1t-mkW62KVEKeqvhApkztYv9kjIZmuITTrMeagyAuBgxlv01ATTyp2XWw_kqkXBvAiOVWlTj_dI7Z75liHRVaxfL_s6RJg4-P5_tHCJaEvcGWVaucQg6NkQRmmq1CtIiMguqb7-tMZW-hOs0kcfLf-gTVnTvzie4BgGSxZEsd4ej0vi7eVDRFs6bbybAyR2DYzkVdCtDebNyboyPoTwTg5TUgOKxVE9Lg8mW8cv6r8dQzIbQTK55FXzPOPM9cVPpDUJLIoQmSRAxXx5mPQ&prev=RQ035BA3C32AF46C&p=13&pg=38)

* Intellectual Capital Resources
* Venlo
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/c29dba403084b3c7?ql=q&sig=e6817a4bfc29070f7db2e8db314404fc39a13200&e=s_30Ii4cXDOaoKBNNGbH7vLhcIeVV2AtiZHDUdPf0CzP4IMMDB3C9776ig5lQUbcE-UzbsFAA6Rg-6maOIom7VgWFcuYweNulB8470fF8aB7SW6gzGV9VV9paFwXdQvZfJ2-z_8HcDUe6G-KrIq2AtvpEO0Fz8LXMn9uQ3FNS3oCYnEIv5EBaDboClKVSVpRAUw_2wjyFr9gBxBh00g6eJFhfc6kOn96e4iH9K1FksLrNs1x5MNR-ohmLBVyDIyy32L6pm-f7qV8xLNHgc-qH8TUVlX2V9_ojF3Ojj0WJLF2XNEIsGzDYZ9FAOjaVbGzUgrn6ZJwN2Ush_RN5TNctFq8pWzhd0nLJyyvKDpn82J2Xab0gkE8DI9EP1bFNzez0FDgfTb7BUrvDQYj4_HWBsBA-SlabSN5418SLB6nDg2-2h1w4I2a6tyeGvKDVFz8zrISLud5GOyCXzXjimZm2nqOO3YVUtUbN0gysjANHFt0y7NDYhfejR1BUb1M6-9nMGqmthF7CcknSzORnf0I2A9aqavMVp-yMo3Xo0HYT3kp9tg6IFBK1pPtZtXU7N_Hao1WQzUtGGJWESw5PZLyHeI2X6TAQyxGjo-t-zWAp2zUscukOsB9DJBuFrx-j3c-Yf45Fni7FNMzBjcrmiFcIxCT2iQk_7iXtzn4PBNBiCw01RsZgexkK3016CnLQIQko-rPsB-rvZCwJl-oPn8LnHJNSseYJ67LISjdnO8l7VKpWrTYIBDL9VuvAdUYtLhSrkCYfpJX0I94OnagQ4ARcKJSi1PAWnE6b_B4-it2EefoU_FG9lZbhsIV1UVuEGTlXzriTuGYR47ZWusnDYMsNFb-FqCX_ORWValTK3qljsUlbpCAUGpZJ-ykSVV-TaF3Aq5rqGoxMGwY6bDFAa4ayWg4Lt__mqN1Lb3Y5vqbRArmRTu6rA5f0izzfE3zNl7BfjYxqJe7H9ezxb-VXe1ZAt132ew6H2HSMfWTrjVrQDPGEewXZNF3kaLgxEikfyqj9EawpuHykrfrLRqSfFoCZOaM-K3cg9CJ_W3wdgiaZDWehdTcXQStCEfbsbZc24Mx13umm76clcaPfbMSMdmgVLhKAPWMEkW__gzElD1gXfmIIUL9k1nDzZofBK0qo1cnO5TdrWTk_rsSPW-6wlmfCprKlr9a91nW-iwPHHTtvi3MS-Sh9wnNz0QYm9ci5FoZt1OEl29yZwvllg0P0HgYUZJdw_KXey0yt4yLsYA4qdKtI1XOI6h2bAhaiPWXBKwlXEnan1Bgk_VSgabh_mR_cNzWJEpAOZg3djK-bM0Tfr5ZJ1II7r2DM9TVil8brpcNwZo2B5hOX_bhsnhF&prev=RQ035BA3C32AF46C&p=14&pg=38)

* Intellectual Capital Resources
* Ede
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/92af4bfdd63dccb0?ql=q&sig=4337e47291c60851a88c497444d5e07f526aa0d6&e=WWYz0V6L8kZsXErenxBSBe7bJSOJgXkRHkmDB6NaWg_sop10Ni22vbDn-bUEwm0C4g7aUA91J-AyoNdFCIiv0756TdPVvfYz7RzcAbNO6llM12CtqD_30IpGiqRQ6YffIu_z4EoHrTpUoRerjq7M3KBh-2eYv5306eZT1ee-5bxws_ZKDSV_hrRjpTY3egRcB4ZrUoLJ_fSLE3EDWe5iVpNbcDl4cJuxVBSprif2HQnfvcra4TwcDrzIznwwVR6C3nmxb3NPZu4HKBFT4g1X5VrTIB-ty741Oo8dttF2XMNAlvGl51S40O3MPHskCyiwfu2JRuvx0wbVEpNTlhj0dLtwBZhef1xr9fdBaYEBHahL4qK4jmQKdoqS8Mm7T56AmGOP2nVUJZq_XZ-thWgBxRYH4YNBpsUBXuYOphS_Y_5_qxn-xzbTLIRHrk813zCCleA6xAtwFxz64JjBazkujCr7ogINRf9qKLs1ZQl1bx_vFLteQU8d2oVKnpWg7lcz6bkU9Ith6JeuU9WWQuWw_nD-MPkoKXP1GuqRs2Lco9-pXvl6-VlbQ2cM884Uo6FVXHQDEn530_XeU6YGVc1OOM4OViCclfp9co2MadD4c0csd2P-FZX2GMaAUWkRyofmQ-djd7_4MqekwDhvO2SYsGCw0h3QnIgxdW0jDWxf_R1jvANUEBbAl7fhtaOBh4-5m_90lpKkZfCQ6Bc_QSxycHwUxtNy4UQl5AvE1hzMBqTBNwMFo4-lNUAvu9auZ_rCzxUqByuagXzOAQgXkTmEYB6CDVOrBP730WycCPOGnLY9vbKoPvCy0B4gfFCnN3LQzEM3EjZAbLboVmnGKMaTwXmGiRYMZEGcKnMq862MqCKSLBjvWtDNe7It_3ET4NmDqpyBpjwbDNgyCaBaoZXRMnZ5d7DMnWkCl7cm1yJGaSA3byrXA9TYPHYbm1ANNuIVqSHyDXRa7WeEaAsboG9ze4T6UwxcjEb91Q1maLXfeBlZxIyioHu64kPh-cQs2dUYVmexdLHcDNZtj6NASqT6RnU8cYXzV_23lKKl6fKdVh63xxjpmsoQraJgdhHaaaOGZH5-CO4vGb2Cs8YQ_NdBO0-gVwyvs4BryRiwCZ9VAXzvzO1jvz600wjMZLgxzrXR-u3IEdf-rYtsPbCQ4JH0T47ItSWqj4Pni2L_xaDWew8kaFyx1dsIuxBETQgAlU64nryAhPTL0E3T_plg23ycTXutcsoht46PwPhneyyn7RQkqlL40XRadAvFbcRGhnImzZLkMHNon22fBSAQCKZVUyqRUTocT_LfCYixrwb-vcYOgawl8_vGk7iH7iPRZFYLouBc2ceJ6uurO7kM&prev=RQ035BA3C32AF46C&p=15&pg=38)

* Intellectual Capital Resources
* Hilversum
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/1564cab837d42bc0?ql=q&sig=3083b6c2a48af76dac7052781272af5654f5a2bd&e=MelsNsU50ux4JfW9hj5vm80vg3SWJDuZKcaWRWudKkQ3xssWICaLXanNAuXeschaVovQsUyhacUfooj4WmFweFEhl8VT7LuD9x3HwDdIAOcCGobxm3TfqRZ_Og2gGu0q4jGxTcXSOd_WUy9xTX6Rf2V9qHEqGZes2E_PiUtcm2ES3pKoxCtQJw-ISCwb9A-4r4vNeILHmbHHOzAEBjnP10Erqs1XhjR3SGQkzd_AWyB-rEekktnCGgusRAqkpiLIn6YHnh5TgepDIz9BIX-PF4mTxw_KfCoCr-_UTghd27JgZvUtkEKgApbIhCnQtimWZoLeiXHE0CRBJXOQYWt6KfsJ605bebXhxe4u0LqC-_lOSQgidvaFevGo1gmQbMAXsMczN-4RzilGxVvKmcP8-DbHgzqkouj4xh5n_K3d5POlGNr40ooiK30t7pQoNsLjkWu3ao1H-kw9yIsn5Qh71M6kqIpTF50bxLf3KNVPhUndMnUje5ryxruDV8Q-UbU3gN9CZ1HwX_1WId2XIK2bktsOn99Dew2erRiBW-nN2m4pzKjbtWGbN1alRe1wLAupec-4pYpnzNNIgz59hO1meNdlmIndrJ1FuxXrtv0yCvvU6bqIFk-hxSZAO4YHNZGy2QfIqq5jKQAWmQoe8bcgZSm2FKV3gQaW3WlAvXP-PKHz9jpu-AD7shCvl14rFLR8OggTxVhXLq3SiFLmUPMHOvYMm3fU52wb4j4-PT8wLwHZSEjd02sRs5WOW-e-F605MKGdlbQbJ4-xR0Txh9oKYpBh3-CROUKVWFw9-9EXCT_ljOrVqELGHFdNMvsIpLwjMoGSuQ2mIJPMQ552dTa-nl7WUigvHRyq2XeThGEbToVSvdi8btCfEZyPJ84NaGHQTjuhljcmeAKyjSi6i7FC-F4SRk6mtkHEThiUyH6MCYbgSAxNq1-gjw6XgwYuTLaVMSxtNMzuHg4qN6hNToy7owJVrDEsjiqQVF8NoTJTABEso7UKZLpgeUTu4inPNJam5HXrHKY7HGKzH48POSXWvlHdA-9JP_vuoUDhRSkVAdXKZVWRhTKOPEhx9_MNrhAc9aKTbo-lzOCp1OuYneVxLiofCMVu2Nxjsq8nxdEJvvogHsoVhp_DVXm87RpTpyXgEzThZ_eP1YsYfpK-ex9j5ti_H4eJeQvuAGQQR7aHuXg1lOcojc3TezugGZtie68Kpxom_dTeevdlu4eQyVsLaH-Uc3RyU9EtUNtlI01KRV-tGZzTrkbaVIG70L54MmAu-AqiG05g_8HIRLnB2TYUOkzZOD53UHFKPq_Kgic65BFbz8hHJ-kc52hZA0MYL7cMt6j9jk7v0N8&prev=RQ035BA3C32AF46C&p=16&pg=38)

* Intellectual Capital Resources
* Lelystad
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/9471ef95bbee99ce?ql=q&sig=04be62124b826552dc1091a53c2f6d932ca748a5&e=j5KMLDukXygSSjI7Ds4KwAUdAGGEHkk7QqIaoMKV2kMH9qac1BEZfduz_57M1HfB9Rwa6OncnIEwAKlpai1xDa_ySTLQydRA8q7TuxbIL_YAkX58qugGsktvayxL9C8IVHEqmxKh3lMNBK8-ocWZ-z8cWc3V7kJNZtac4a7c_H6x8-kf1ejYwbOgu6kV6LM2VDK7PIn0dQuHTZt2ZkPO5SS5N2LwbIj73r5E4I-YIt9_YwkkD5sigmaL18bhauB4EyxJwzQEWdq7jzKcEc3qWS_ltqH3yJzIOpYZeME5pLmMyWLXiPskvNGKD4KQ9yjpF7a-vrjERAYpC6yfIMQz7T3rl7QnIDWpXC-hEkJcOQeteXRgQY_xuUIwk0L6d2gXta_Y3S1UTviKplfjRaDuVfsuXmv6PlHVMEm6aWo3xKg5kcyr96Ao9cJJR-Y-Dl38JyQ09iWlvz8wL5drri7qNBCLMEWHbSS8uguz4agf0szKyllq--nE9fvlHaL_HYQdPMOvT7gb2-XH1Jz9-w7M4HCn7nwvyx_A693ClApx1BaUecDzATwBXZGXMzWYSEJVeB1N7YcWUC2c1pXqYQfUSu4fg25HpcJAEn6Q0n0IrTDGRglaLK0T3ffK0mq1_0YvLXpGiuW2MOEoMzXuJlssCUhTGOQamMp8glZ93Bt24W8q_8PZgF6q4BXG6duUWDSf1N72QdjU8_9YrgeOGcUZqWEiCJccFjVpKEno__MmwaECiABEBQOgLOh1WZ-3GiKSlvFtkZKXkop5IcJ11h_4xTPMfuCjAmXmPKR6wckstPSMNz8CXVCLy8UJxZxgMqq-pYW1sVffsWypgGpCOduNIs-QDQY2lxaj2Rbk3WjBy7CMfDUa-alGwuyiO7Sx8-g6oET9sO3xXrhxIDhuhcc1xt4KaPRuvuILQkLy9I4SHnKZID1VbX5OaMP8fio-LpMeXqAdDvWiJitKBpdKVHK2CUl69ZuLieRfJxFNppc7iG2AHV4ANFmHeRj2N7JW-X510-ZCk6QM9EIkRAqz1ChadkOSgNh9_mVg8nu5bt_cvsug0IF4NFYluu4gRCWTUIqEmccEOxEzPCoBBdM2CnUdwCAgzdrF7-xpanFo96OJyiTZmfAx4lRhewLeCfJeqvZ8__0DExztTT_eltmTc74GllxxNHAHS0-g1DxyC0kl7aDd7NdppKQI6FB4baI8wtk_T6BbcZJaweD4uireGCyaX4R-x6MnBAbCR2ipyOlA0lTInzNiPloGwmQ2954AvXulw2a7nqVHDmcU4qEAsiu2kOac-MH2dxEUj5weYTJ_sbomzu8VPgeqmvj9sObmnptqCN-NLkS5LxFPaCkL&prev=RQ035BA3C32AF46C&p=17&pg=38)

* Intellectual Capital Resources
* Doetinchem
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/9c034676004ca98a?ql=q&sig=20bfe3cb118218123a7ca64f9bf0ef8f29a8d570&e=LAFxI2HOA6CWPZmI5PPNTYej1g7jn5HtR3hxtEX1ln4SpChmaS_XGLqJMdJHMOdmZxyJxn14etJV08G-VMrxJufNHwWDWRHmaQH8FhKlm-EQ2-2QwEfCV8DbmCXNdiaMLbkhsqwhjuP7kLzQgTRmKQhrZTwaWDdMHz8XbaL4-tWhIR9lf2nqA5CnIxxqi-UX3pIHNatGnFP16d9mc972L_ZNHwMQcHZPFDZn3m_MSARzXjTb6lS7j7qrT8qf-y_cJkgINzmSH3xBem_snDlmm6RZtxU0g0H9MC4m_JIqpK0M_2K35cQFJ46WFEB3lnKgIANkZpZHBKgcaKrTOQRGfa37ltbkbt59Km_Gq_5btczfRAymS_25sMZaxaCFJVpAgJt29keia9dtdsI-lJkzNi0zEWoMzijo4TorjhWk5gw_TlYNXU7hfUwgRXhOxgffxc212AZ0mssmWjWxCNZIenhtmIOayIFBPEgwgWXlWq9IXXurI71y7f09f0g78SL-C5HXn3aD0xYZfIh282I45X0YwHsIEtWkSeJrl373hdTfdBYx7vteoFtjey5TDJD6ZYH45r91qcHGD40pnnOIkeFsdF6zDlrUKVmuvpnJTvy-zPx20JkcvF1hJ20LxqGctkxvZ4nF1YlDUjid350GQwRCRQ36uyq7q27s8nAy_MxVW5QUGACXLtJ_wjs4MG9Qo-5p8tYtkGg_QOaFPq58OkOU-RrVNNGUVdngaYJnWmpJ_n5Jq95y6S0Mjt2e7kecXA4sUTay_zVgg2PYmKhGic6SXNIPNuQ-oh3Pz288-UJIMYoipuUZ8wKWo2OfOaUKtjTKG7haN_D0q2f7c9JbJwi7UaG6LfSc247L33XSvQwjEkP1i_IBITtX8XDcROT7MuXnEoS7VnVLQPZIHewxmE6L2nazBy6qyAaydn2pQxMLvPtloKqdmIcsDA1bw2ctkJhMWa8zFDkqLacoaQbOSa7G6sJp_VS_r5A1IkaqIzUupNxLe3s5sQTB4Dyq_toQP9zIoWqqDZ3nhAiCtGIoBJHxgB7sm4BRZmDeDn3tIR0e5MB18tIZTOHeoT0tqfVNh2oGxcNuljRJU0hZKsmFsud__P34nxMYolzUKkdFEmAj3PJuObwkKKv3kriTnNUohs2FiLkfVzuoMUqi0EgdTRRXSBDqrjKBT2gYiplmk09mSLGObQG0QQ5j6Fb8gp-lWRAn6APB5l0SCJVq1OYRrYkz7EUiXMDVkoRQLVM2pqZtmDQwUbBHG7S2Tu15c6jmwRIGlX92i6KteDUld71sRxRWSn-ywXk58m6hip6ZFRvck-2DoPXCZ9fyUl6oIgBnU0kPANd9QDE&prev=RQ035BA3C32AF46C&p=18&pg=38)

* Intellectual Capital Resources
* Nieuwegein
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/eae51460a87eadd1?ql=q&sig=2c95c16b93c178845188cdb642bfd3c38c538c4a&e=Co08YxnL-cHS2uROG-GOvxqJTtcnv-3SkVGoLjtrln0j8kZOwvFEp5_Y_V5d_oIdYODDp9ZRj0YDyPmKIbO8VQ4FGwLFNfCdAoJHO9UEAwi7xde3jX9MC_ofF8CBBGq_b9rtso-XxW4hxpgTvDzNbA-7ggJOXn23N-ea_bV5JoaxNUKlCEca4lpJqWM3AGlkdCzYt9hGRv73bHdYMH2tepK-EBHvOdHt1hk0fYQxiCC6FJ0G-XfGUV7xwUXGoUx8eGWZpojNR9B2REn38NfnGIjDfTUk56bNjbc8UdEXKQgBAo0_Jk4PDHpfCvtoNKiDnUO1hlmIXx0sIqoj9KCt3nn_6EmFkJi0USo7aOtq4ZHnIP5I2_WO4834YSoD9BNK3m-JbXbzK_LrgxjXqXo_nae2ryB22xwwUdNkzNgEmm1AdCCbrUnR5Jckb6K-HCNcA2fbPtGR6QgxkJjxMOoUjpagQM82SPILED5kE5Is-p2UiuWbLiG2BB8yL6st8AHYuLki_o_fKPAS1p1UpP395lEP4zhYwcsXDedcHK8b266TbgaW5u21nCq3uhSIszz4qiqbITZhJ2Q-Io-8f5KSEvTuezzja6XqTN2ZdN0yHFFdGa25EMElT-dpExaPE9wn5Vz939pTxn_UQhMYuZOqd5xxZFUDuJYWyvMG2hMJrl6-zmEOKvUMOJ_wHAAO9dZh6qq7xnpGjt4zU9MB-OrUpVS0fH_3t_eiEjcVX1y2Iy2NUnGwnRM52jOcuLsh2CX1H990kV8wokcl7uIU6jAl7z8-YCRrKCbu3SJoJr2arBiRDU1QpzIjtUV81o_KzRUwoNOoBRnFwQLevl1IsZOXqb5lYpyGS-OS-3I7b_EdD2C8XhoJoz2DFYi-tBU5fzASJkEYNoQWn9VOXxeQo2Cl9guCBNgRWiL0Qk6BTTwmfJiMg8xyFMnHC3YqPBbGXxV1GVNo-kdxd-b9opyZv8RLhON9xeUU7-miMaeyvq8o1gLttrFgjfJBbGmgN0sp8GgKVN1YT2KLLpWS0Y-UK5670DubHh-bde-mIb-N3Tk4zset0txhEx44LS-AT1dB1SSUPKOpme70P999gmJ4k-3y6g8oGooTf-GSTAvtDyClyY3jVO0dhPOvsXpqgRiYOJFvDDMmEeeA1lxGH52s_gSRFHAlPp69y2SqWnGQA93aRroSVB0IsNyvNxgDx_xZpRqS5tJ2ava6ec7ga4FDA4bJgeIjgykgAbDwczg01mcljSLyjTVXMwSGI_Z8Q0AXQC0-4OUq3ODkY_njbt0ChAeXLbGBXJYvYLWtBB-Br_FBB0tryNhd6ZUm2Vs8_79nQDm7mXXokK4TzZw&prev=RQ035BA3C32AF46C&p=19&pg=38)

* Intellectual Capital Resources
* Leiden
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/1dbe7e963f419599?ql=q&sig=fd21676524b8c6a4cd61796525d47b04f1a5737c&e=AlcioXh9fldSCmSIuG9SB0EC1euaKQWrFt-EjUEg9lxr9aY6AdTOcCYqikDcC4tRzZs5ZB1LcXAcjEbSU5w6eQb3PgwEUrJhhupnBfVd1eHEv60Y7WrHRmSvwr9aHTk1GJcltf29EPTwU_4CXLjyZoaEVInEUI8Dz-DxddHo2EBvCbWvjgU_7vI7gGSkceMhIti1bD7-Ls0XW8WHSCDzSJsv750-RgSYdGNyVfHRsQsBGZLrC_Gebv8sSRDOTSGkH528zCcOS5BI-2-oolmCN0haFKHXrfQQHI-akrYe6EPTDJ_1g3Fpjx3aXRmnAohf1Ga7lorZSKVWnWo_acYrIwHATHKmtLxkBiTVew-fCKBZUUj2kF1_9meot6e139SsN42ijzFYTxuRt8R8b5XVs7NAh8OnfhepMJ95L0GBA22-qXaGnOdK6kgR3_oeGZh4MOgd_eVTSvQMueHAk1vbhJZQfBdKDSuFwvEU3cqrNnzXVkKEV682s79XzylZ-f-05s7W7jfsHoqhi8ioZvcf1Harn0lL35KXLlxXl8yROsd4bqCpAZKMEqo97YC1CSjadgCPisbfZ0jdcoI2-0j3yrN35ZdFcEHY_Qmg2_18H7azt2rG64C2V2pWe3IVQCZ7QixU7ils5ZiFTDoa6JAitocP85cmEb6bCVxMQmtg_f0XdptMm70c1kYBK27MsmBJY94GYaMByg9BDR8E6MPlGJH6QbUoXHs4Xqg3QzPtkxlOBF8Gu1rQn1MGEIeg9JGPYE50CFFQtE_dHotnrighXjQtISDpeF1i4LPKBm-WRFixm8y_748L8eh9jsXG_sLHe9EpW86Te7QEh8mgEOu62zYjfG26rqBPzALrj6iNosSWWVIGJJo_gIqhYqrApsvYObbyiucILxHCQCs3g0B--0daNmhgbFybpEEI4P6UYKsL9gA9nBTU3cnSEaUTdsFWW5gYuW5OGBTdV6Q4Wv-KlGrpQL3dBvOjdHEeSNnc3wTJ6CafnDNy-muLEyM9JbRnftT1XXZ8uQWOv4CiZKIhYaYhbdAJDj4Z1i2MXfHwoPlrDYVwNGNAP--J3x9Z2oL9gxD23TE6rR7dRhrr54Tpfe12sjzRThnp4jEwKZJzV9KDvZvHx6bexWJI0G6XwIqiAcHejT1L9dvAaHWJOMkKKdGd90EDlQH8-DrJ3ZmI3I12p6yBWr1X2LFjNXwnIR8KV_O31L1dutOPT6KS50qLA0SgFKlpgKG2GlWHEwRL2_sALdruqjxdtLR2rS47lVCYMddEqpbdMDG7dfhjncURHFj2ewatL2e6PfBNT46W5vyIfDEDIMGkvnFIu8Mg7n4bQp-r8qIH-d8&prev=RQ035BA3C32AF46C&p=20&pg=38)

* Intellectual Capital Resources
* Delft
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

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#### entry level in Cities...

* 2063

  ![Amsterdam](/public/img/coa/nl.amsterdam.png "Coat of arms of Amsterdam")

  [Amsterdam](/in/amsterdam/entry_level "English jobs in Amsterdam")
* 243

  ![Rotterdam](/public/img/coa/nl.rotterdam.png "Coat of arms of Rotterdam")

  [Rotterdam](/in/rotterdam/entry_level "English jobs in Rotterdam")
* 241

  ![Eindhoven](/public/img/coa/nl.eindhoven.png "Coat of arms of Eindhoven")

  [Eindhoven](/in/eindhoven/entry_level "English jobs in Eindhoven")
* 207

  ![Utrecht](/public/img/coa/nl.utrecht.png "Coat of arms of Utrecht")

  [Utrecht](/in/utrecht/entry_level "English jobs in Utrecht")
* 162

  ![The Hague](/public/img/coa/nl.s-gravenhage.png "Coat of arms of The Hague")

  [The Hague](/in/s-gravenhage/entry_level "English jobs in The Hague")
* 87

  ![Breda](/public/img/coa/nl.breda.png "Coat of arms of Breda")

  [Breda](/in/breda/entry_level "English jobs in Breda")
* 87

  ![Delft](/public/img/coa/nl.delft.png "Coat of arms of Delft")

  [Delft](/in/delft/entry_level "English jobs in Delft")
* 78

  ![Venlo](/public/img/coa/nl.venlo.png "Coat of arms of Venlo")

  [Venlo](/in/venlo/entry_level "English jobs in Venlo")
* 73

  ![Tilburg](/public/img/coa/nl.tilburg.png "Coat of arms of Tilburg")

  [Tilburg](/in/tilburg/entry_level "English jobs in Tilburg")
* 62

  ![Lelystad](/public/img/coa/nl.lelystad.png "Coat of arms of Lelystad")

  [Lelystad](/in/lelystad/entry_level "English jobs in Lelystad")
* 57

  ![s-Hertogenbosch](/public/img/coa/nl.s-hertogenbosch.png "Coat of arms of s-Hertogenbosch")

  [s-Hertogenbosch](/in/s-hertogenbosch/entry_level "English jobs in s-Hertogenbosch")
* 54

  ![Haarlem](/public/img/coa/nl.haarlem.png "Coat of arms of Haarlem")

  [Haarlem](/in/haarlem/entry_level "English jobs in Haarlem")
* 47

  ![Maastricht](/public/img/coa/nl.maastricht.png "Coat of arms of Maastricht")

  [Maastricht](/in/maastricht/entry_level "English jobs in Maastricht")
* 45

  ![Almere](/public/img/coa/nl.almere.png "Coat of arms of Almere")

  [Almere](/in/almere/entry_level "English jobs in Almere")
* 40

  ![Apeldoorn](/public/img/coa/nl.apeldoorn.png "Coat of arms of Apeldoorn")

  [Apeldoorn](/in/apeldoorn/entry_level "English jobs in Apeldoorn")
* 39

  ![Ede](/public/img/coa/nl.ede.png "Coat of arms of Ede")

  [Ede](/in/ede/entry_level "English jobs in Ede")
* 37

  ![Roosendaal](/public/img/coa/nl.roosendaal.png "Coat of arms of Roosendaal")

  [Roosendaal](/in/roosendaal/entry_level "English jobs in Roosendaal")
* 37

  ![Zwolle](/public/img/coa/nl.zwolle.png "Coat of arms of Zwolle")

  [Zwolle](/in/zwolle/entry_level "English jobs in Zwolle")
* 36

  ![Bergen op Zoom](/public/img/coa/nl.bergen-op-zoom.png "Coat of arms of Bergen op Zoom")

  [Bergen op Zoom](/in/bergen-op-zoom/entry_level "English jobs in Bergen op Zoom")
* 33

  ![Deventer](/public/img/coa/nl.deventer.png "Coat of arms of Deventer")

  [Deventer](/in/deventer/entry_level "English jobs in Deventer")
* 33

  ![Heerenveen](/public/img/coa/nl.heerenveen.png "Coat of arms of Heerenveen")

  [Heerenveen](/in/heerenveen/entry_level "English jobs in Heerenveen")
* 31

  ![Leeuwarden](/public/img/coa/nl.leeuwarden.png "Coat of arms of Leeuwarden")

  [Leeuwarden](/in/leeuwarden/entry_level "English jobs in Leeuwarden")
* 28

  ![Harderwijk](/public/img/coa/nl.harderwijk.png "Coat of arms of Harderwijk")

  [Harderwijk](/in/harderwijk/entry_level "English jobs in Harderwijk")
* 28

  ![Tiel](/public/img/coa/nl.tiel.png "Coat of arms of Tiel")

  [Tiel](/in/tiel/entry_level "English jobs in Tiel")
* 24

  ![Hoogeveen](/public/img/coa/nl.hoogeveen.png "Coat of arms of Hoogeveen")

  [Hoogeveen](/in/hoogeveen/entry_level "English jobs in Hoogeveen")
* 23

  ![Zaandam](/public/img/coa/nl.zaanstad.png "Coat of arms of Zaandam")

  [Zaandam](/in/zaanstad/entry_level "English jobs in Zaandam")
* 21

  ![Sittard](/public/img/coa/nl.sittard-geleen.png "Coat of arms of Sittard")

  [Sittard](/in/sittard-geleen/entry_level "English jobs in Sittard")
* 19

  ![Wageningen](/public/img/coa/nl.wageningen.png "Coat of arms of Wageningen")

  [Wageningen](/in/wageningen/entry_level "English jobs in Wageningen")
* 15

  ![Echt](/public/img/coa/nl.echt-susteren.png "Coat of arms of Echt")

  [Echt](/in/echt-susteren/entry_level "English jobs in Echt")
* 12

  ![Groningen](/public/img/coa/nl.groningen.png "Coat of arms of Groningen")

  [Groningen](/in/groningen/entry_level "English jobs in Groningen")
* 9

  ![Ridderkerk](/public/img/coa/nl.ridderkerk.png "Coat of arms of Ridderkerk")

  [Ridderkerk](/in/ridderkerk/entry_level "English jobs in Ridderkerk")
* 6

  ![Roermond](/public/img/coa/nl.roermond.png "Coat of arms of Roermond")

  [Roermond](/in/roermond/entry_level "English jobs in Roermond")
* 5

  ![Moerdijk - Zevenbergen](/public/img/coa/nl.moerdijk.png "Coat of arms of Moerdijk - Zevenbergen")

  [Moerdijk - Zevenbergen](/in/moerdijk/entry_level "English jobs in Moerdijk - Zevenbergen")
* 4

  ![Emmen](/public/img/coa/nl.emmen.png "Coat of arms of Emmen")

  [Emmen](/in/emmen/entry_level "English jobs in Emmen")
* 4

  ![Sliedrecht](/public/img/coa/nl.sliedrecht.png "Coat of arms of Sliedrecht")

  [Sliedrecht](/in/sliedrecht/entry_level "English jobs in Sliedrecht")
* 4

  ![Zaltbommel](/public/img/coa/nl.zaltbommel.png "Coat of arms of Zaltbommel")

  [Zaltbommel](/in/zaltbommel/entry_level "English jobs in Zaltbommel")
* 3

  ![Edam](/public/img/coa/nl.edam-volendam.png "Coat of arms of Edam")

  [Edam](/in/edam-volendam/entry_level "English jobs in Edam")
* 3

  ![Middelburg](/public/img/coa/nl.middelburg.png "Coat of arms of Middelburg")

  [Middelburg](/in/middelburg/entry_level "English jobs in Middelburg")
* 3

  ![Terneuzen](/public/img/coa/nl.terneuzen.png "Coat of arms of Terneuzen")

  [Terneuzen](/in/terneuzen/entry_level "English jobs in Terneuzen")
* 2

  ![Hardenberg](/public/img/coa/nl.hardenberg.png "Coat of arms of Hardenberg")

  [Hardenberg](/in/hardenberg/entry_level "English jobs in Hardenberg")
* 2

  ![Kampen](/public/img/coa/nl.kampen.png "Coat of arms of Kampen")

  [Kampen](/in/kampen/entry_level "English jobs in Kampen")
* 2

  ![Langedijk](/public/img/coa/nl.langedijk.png "Coat of arms of Langedijk")

  [Langedijk](/in/langedijk/entry_level "English jobs in Langedijk")
* 2

  ![Leidschendam](/public/img/coa/nl.leidschendam-voorburg.png "Coat of arms of Leidschendam")

  [Leidschendam](/in/leidschendam-voorburg/entry_level "English jobs in Leidschendam")
* 2

  ![Naarden](/public/img/coa/nl.naarden.png "Coat of arms of Naarden")

  [Naarden](/in/naarden/entry_level "English jobs in Naarden")
* 2

  ![Schouwen-Duiveland](/public/img/coa/nl.schouwen-duiveland.png "Coat of arms of Schouwen-Duiveland")

  [Schouwen-Duiveland](/in/schouwen-duiveland/entry_level "English jobs in Schouwen-Duiveland")
* 1

  ![Bussum](/public/img/coa/nl.bussum.png "Coat of arms of Bussum")

  [Bussum](/in/bussum/entry_level "English jobs in Bussum")
* 1

  ![Goes](/public/img/coa/nl.goes.png "Coat of arms of Goes")

  [Goes](/in/goes/entry_level "English jobs in Goes")
* 1

  ![Hof van Twente](/public/img/coa/nl.hof-van-twente.png "Coat of arms of Hof van Twente")

  [Hof van Twente](/in/hof-van-twente/entry_level "English jobs in Hof van Twente")
* 1

  ![Lichtenvoorde](/public/img/coa/nl.lichtenvoorde.png "Coat of arms of Lichtenvoorde")

  [Lichtenvoorde](/in/lichtenvoorde/entry_level "English jobs in Lichtenvoorde")
* 1

  ![Oud-Beijerland](/public/img/coa/nl.oud-beijerland.png "Coat of arms of Oud-Beijerland")

  [Oud-Beijerland](/in/oud-beijerland/entry_level "English jobs in Oud-Beijerland")
* 1

  ![s-Gravenzande](/public/img/coa/nl.s-gravenzande.png "Coat of arms of s-Gravenzande")

  [s-Gravenzande](/in/s-gravenzande/entry_level "English jobs in s-Gravenzande")
* 1

  ![Winschoten](/public/img/coa/nl.winschoten.png "Coat of arms of Winschoten")

  [Winschoten](/in/winschoten/entry_level "English jobs in Winschoten")
* 1

  ![Zwartewaterland](/public/img/coa/nl.zwartewaterland.png "Coat of arms of Zwartewaterland")

  [Zwartewaterland](/in/zwartewaterland/entry_level "English jobs in Zwartewaterland")

#### entry level in Provinces...

* 2441

  ![North Holland](/public/img/coa/nl.noord-holland.png "Coat of arms of North Holland")

  [North Holland](/in/noord-holland/entry_level "English jobs in North Holland")
* 974

  ![South Holland](/public/img/coa/nl.zuid-holland.png "Coat of arms of South Holland")

  [South Holland](/in/zuid-holland/entry_level "English jobs in South Holland")
* 779

  ![North Brabant](/public/img/coa/nl.noord-brabant.png "Coat of arms of North Brabant")

  [North Brabant](/in/noord-brabant/entry_level "English jobs in North Brabant")
* 369

  ![Utrecht (province)](/public/img/coa/nl.utrecht-province.png "Coat of arms of Utrecht (province)")

  [Utrecht (province)](/in/utrecht-province/entry_level "English jobs in Utrecht (province)")
* 365

  ![Gelderland](/public/img/coa/nl.gelderland.png "Coat of arms of Gelderland")

  [Gelderland](/in/gelderland/entry_level "English jobs in Gelderland")
* 286

  ![Limburg](/public/img/coa/nl.limburg.png "Coat of arms of Limburg")

  [Limburg](/in/limburg/entry_level "English jobs in Limburg")
* 205

  ![Overijssel](/public/img/coa/nl.overijssel.png "Coat of arms of Overijssel")

  [Overijssel](/in/overijssel/entry_level "English jobs in Overijssel")
* 110

  ![Flevoland](/public/img/coa/nl.flevoland.png "Coat of arms of Flevoland")

  [Flevoland](/in/flevoland/entry_level "English jobs in Flevoland")
* 67

  ![Friesland](/public/img/coa/nl.friesland.png "Coat of arms of Friesland")

  [Friesland](/in/friesland/entry_level "English jobs in Friesland")
* 62

  ![Drenthe](/public/img/coa/nl.drenthe.png "Coat of arms of Drenthe")

  [Drenthe](/in/drenthe/entry_level "English jobs in Drenthe")
* 31

  ![Groningen (province)](/public/img/coa/nl.groningen-province.png "Coat of arms of Groningen (province)")

  [Groningen (province)](/in/groningen-province/entry_level "English jobs in Groningen (province)")
* 15

  ![Zeeland](/public/img/coa/nl.zeeland.png "Coat of arms of Zeeland")

  [Zeeland](/in/zeeland/entry_level "English jobs in Zeeland")

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