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# 5942 entry level English-speaking jobs in the Netherlands

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[### FPGA Team Lead](/clickout_alt/1b37cdf973794ba4?ql=q&sig=1735f7cd553fbc41c8bde6c550194e3f239dd10e&e=Z9cDt343TnOFLgwl3lxiAScOnOhyrzNgbdSTcRj7YnPGOvCJCnSv01zHHQpRaVu3sEi2-moBWQuvVWZIKM8LlY84Yiom3DfVm8VOsbX0ZWh7DyXpVcmbnH-EpbvxISTYMRQVp_P8w07goiajkJqIh9cNeZSbpt0jndQL_DMSRD2QutTb9zoJmfXdIcEx9yIUI3BDVsG7-qfFxOOF-UQ7aXOC-LBlgc8A7mf8KIOeANL_HeaiKetX2SL7c7TDtoymwc9tP4KH23XbDd0ypGsEQ0IO1Mmr2F8UDOpps5VTgHWYw_PSjuCe749M_Dak0YivY__62pL5SczTdiRyf7PLwhTlsp4eoATCdbVCJa-IjqnV8Uvtp_3RIGrrr8UTMIa9MLiW3Z2tqmP-nIUIgq8l9LbUXDvp39wMG_hxMQapHYbJGPN1RYf46NpsMIdmi2kGTMQ1U10D_J4xh1dQo_cAKItUH94sl5XHpUdEWb0Q3dTac_ETF0-3AyPU66Oti_YWJt4shXr7QY7gDYTjrFJ8BB9cxmyS2Ek5dQH-3T7iNZhh3QsQRnBPu32NFewvKaGFjHgvDnsn_sAEUAPWgm-Oy0YZtnr3oEZsJCsZbm0Ms09ICU9KYRA5K3_XdP1gBVOmXV7pTK3rA82hDiIvkk14VbAOtczoky2KlXtvazcNyHhcz67pOEYRzTbZeuFpP5f5M_-IDcM9jZq_2S5WNhpt91c-14hjP5nBeFlPg0g5wn8mmbyo0qkaeiyZVJuX0LjmDkmmffwpFpfu9IC7vlYb1GESbSq92AaEiQir1lR_ytZxz92-hsmZmEa7710ZKgJMhjkJXh6VLp4aBDORV8HCrJtFp4-bRUz9H2d23cFVH5hogq-InGwGj0ejynjOLV9MZkiJQpM2S20XdiBOR2ai-OUSO1sFzv58snWCH_UGtTPPsrLDQhKcQF1dIPaQU1S4pIxivsAg6As7JEfe0wupjZuagFA-XMMPLuE5xjNS6kDyrq_7-SIPCjwxKCSBibq16i7G9HnXqmuepqSv8suikliKDXvi0AqnVj9xuLx4PEd55EY89fg3FAoLlbg7XmQHMHI1CdjNuwUQhjxJ6qMT7LyA5tP5miDojdcYG7DKzre6kAP8DVDhha8FsCEnskUbZmaEWi0SKPXQGVOU1Yaadl6oK1fwOQtcjT-AlX0B_h-0iAbSSOXr6O1Yzl6ygMQj1ywjrG_jyqtL6Km1dyD4GzS24Qvm03GroRNTXI4rx-sdqu0es7Wl6b3vMVFqWRVY2cgGOwxvt-Gfd1QWDvt4vb_liF4JXAtFCb2OzwAvzpnPzgOMId_XFYvZiHH25gbxB7VFcQ7FSj2b&prev=RQABBB60CA98458C&p=1&pg=39)

* Intellectual Capital Resources
* Enschede
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

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[### FPGA Team Lead](/clickout_alt/371e0d8e71066a29?ql=q&sig=dc7a2804ef8e8d9b5c7f9041abea524be22715a1&e=Cnacv4nFOyz3ozkuYfnB4fCFcdBwl5hCIRHPKBdUP_rsf0OUitDRavl49oNgIgwSJvrg07laS0xry8Mr__dWPux1uGUf09awD4UELyEnzNntlpGKheYt-04yJKaA3XEK7aUpcHDz20C5OKRwYyp47YLPQnFsL68UlyGYIrQmz4gDyMww14oSCrOUjbQLx_1Xxa0lxrGTL9EzQzfjfI_1kPV4Cse2TepAHM1Rt8kqArEfEsJLJVvZiwVWZ_4NBEmT7fYP9suT-hDQ3bZMWna42ma1J8bISxvTEJFauOoL6ttx4kd7K-NFPLWYIBVQP-z4v4xRmAHPUqE7kvn_tibJib1E-1Oapk5Q-0V_rgQ6v0nRBqzYWa-9-BDlV8LGTCQG5vzWDo2yLxlVA5Y9dJShjrzRh8WXpYPXGOiUnZ69GXfAvbwcneKymeaaGsOnPgHgXRM4n3EgDskXQyygO1De0GG0fElINvklQD2ETb9V3q0no4Ktk66Wy5ohndAT5S_aBqg9JyGR3omA1HV_FrrumA9gqSUowHS1N8OTTbfmZ82sXUpFppqAUkd_CkGCEJ4oojl3bbVL5vWPwL6SlGnXRatkwO0oWNor2wUpD7NUexZ2dKTLRPXMSnUuh968IHW1NiqURGJTHWrDl30pSg8ChJP-cLgaOLqDqWEYdUKCougXT0tqM56dJ-9rfjtnZp8L0e1nlZ-FCp_48lQHfczH7A4YRmRtu0bLOhvkdaNWbGNXKcW2LxT8WsryVGEtaAbNaVmD6beTcShABT1njckNELa9Gwx7rhp4WqTnNsN0yg-0XNZbdcmirGxFwo3OnXKUuaMsmEHnfbUzKa1H8YvH4mNdV44iJ16xowGAq0fyk_t44bPIZn66g6-2eRDyURP89_zOcnB1KsgJyHrxDyjBaxNDBzydTk04Ovxp6NKyzw6kTEFdxaRPHYQ0ZxrMIhoc4Xr1JVv-QWCXhUk996oJcbjKHSzHre1Wyvrgv6nOoNrPPTpjKBMSBA9QgxDYu-Mqh_UONbNLuLgiVIQ6w2rBr3Fr_CQZbalc1abv3B1TLa8sP0mxiU6f0_qBHbdDTz69fEqZZoPeAEEH_gE2oYfsc_ejp6vf0-DLsSHk6FODj9pDu8Yt3WWrDY05qMuSp6fFNZnubK-JM32eG9QA2IXAMr-ghpKGtUi3YI5B-eR9d7rJDSyKPM3pJhwKvjTzkPlUYYSPf1hbKuTDA3o90ZNp92zoZwDQwUJ79Htnn-8XgOEDR_mkS6-FLK1a3UvzUIy0T5Rrp3fWcAenYS54PRWH8nnDN-PXsrGKg2bQHlyKS29Ikc0xj88cRpF8NqwBnHDpRLgPkNClLkQ&prev=RQABBB60CA98458C&p=2&pg=39)

* Intellectual Capital Resources
* Deventer
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/6a95ec1c7afb61e7?ql=q&sig=acb39fb4bd4df4b5e200aa928abce80c28bed66c&e=fF0PufpIPYVkxFb6r7qQLD3iWmo0bLCyrvNQwHTD60riiPC_7yT5tIdp7nytkz1-uRYF0prSfkqQKeZQEVkNTRLDqCC6COmCEACdfIcRm0QT-zbgsbm0pVB4uHMSkXpzIxJNJJbckPlccMKsALCoTc3E4edi19jmgflwkIfTePDeIdR_7hGtq86BO971sBV1AjJe_ZGVg0TNczQf7Zi5Fe1t7QLehLgL4AeoWoh8p2JFzmObck60nEle7rM4DR4bLLFx0LvNA9u9zYzkowpmJZoxkJqMoNy2erQUOx926dAa4KUI0QHOdkORMPkACrtBplKRXS_XHpYzouSHCHuWMkvotoFEh_ygjS_rETyuzl9YBHa2qhEETuEVQZlFevRWN_s4G48A0v9a2E0pZtJiPeoRD5swsYsXCCUgk9prl64ZtePS0-gqZUCf9t2XM8yJZPiOzT4K4TJBGfBZZAT6_BHZorhUMgEkgaP1_VoAW5UIRDXUzS3qp2tvzo3qQB_04Snky26ONjwHQSnxYn89anChd64gAsXVvwktvkPNO__rWWsmwyvtGJG7qxg7q-DIwub4vFq1XGTOV5BELNBQTt-J_apoG-RbCl3C_SfG-nPMckks9QStSa-6F539BYaJVrKbx9_uAXhy8MbS30MVNdaUSMPMIBITRNaFcASO_-yNxS5gaoFkjvkgIssgKTbGmGgDRlgdiFKJ2LtMDANA6rKUIB-0FXhhiGKsHnSUx9LjdZCY9bk0tXuvbzxJ6-_Ld2Xr0egGHX8drlC7jX313Z0-s1W9E-FS60OB74TDOwEoNE8mcVBJNCf_sKqvA3mZF3wb7yJc7xg59rWVHFo36EA7A1ltsUbSMJNezCCQD-uyfiraPZKIGzd77x7y2EBWoQww6msWunlw7JgEzEk233fvaH-N0SCDFeVZVm3_A_x3UM_DUXVnNd3mNot3IlIaUkKWss8fagGrhStRXXl4xJ7yT8q2OyhJWHOL1HncWfKtaG-d6Knfpl4O5AthAFU-0P5OKx_GWgrsLVyn-IZf_vJjq-MK2plPuFN9u5wT8BKgdPRNwZJY40XbgS-c7G4khOwKe2q9OB1qUww_rUPop0tu1oaGaVRTgqxuQ0XKOdAQ27L9rGW1ZvlxU69vziD1hSXthUSkGg88-f4sYud4F-jfsTsrp4yuLQ0_Lh1kObkwSL_sl276lu1LQUF-Q_iwImn9WRTrAfEjVxWtu12WjToVIAIBUx4EFqS_4m2acIcafbtV9GyXeBHIdGwZfHJQJKaQtUccNOHQCjSTI-JcUFTT6n1DJu3d_Fj93RMuIghu27P6B921_ctLhz27qHhMtFO--9gH23A&prev=RQABBB60CA98458C&p=3&pg=39)

* Intellectual Capital Resources
* Haarlem
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/f169c5490c4084c9?ql=q&sig=4fa058b71adab2b425b157fdd8ff0cabb90c89d4&e=OL5OlBJm6MJ2VclIFu-ViJLJoJlxggv8V2OSqg2dkVXJdLDGybVuIrkrVkd8f0Kc2antrcLmgUYrU5F8TkZtctg4NGCxIS661BE8bNGKR9HlwXka97I0auoFDEPMWtZ_KHyAerjmI_s5GBYTpByyofbqalGqObe1ha5r3Pdt5A5s5Yf30oF9hYkOqQ7R2dbj-2KQdYBr7TqILdDdxhxNlnINEQE3aAmhtVS1tsd7wnJ3-w8-EeZSk4MTVfSFC3uETUetpg61-C4biGi3e4uKYcnKlJvwSabI7mmLjqKOROlrKvVSw6qt6-_tsADxz5GImK9X3sZLr06NBWjEtg6ce4TQogHkr3seRgMCqu2mHvVCuaHHZ6oSA2jQYZ1MQ155b30hp2RhjmWtx4qw4iRERTMwdFnvVYNPpMFlif5XhYQOtJI8udI85oQSLyIQ-oIx7G56ccMYh_kVDnLFsS-ZWidiLRagoncl0CzdPvfmuEzBtWLqPY06O7Ccqakp5tGmfa1vRTulldXmi4VNxvwsydSAQj3gE9mekZrw3UhPMPrS7qwj0NmaIUzC3aJGn7VlszsnUSkODeNlo2tl7wnEU3l_okiAXZBbGNZG2eM5mLyLhxLlr1l3X1Uo6PThxk5LFRfGxIdVqzqdINhbmGu3pHkGYwDYYvWVhp2RYKXxv9jCfAsbaESdSp61er-qG7sdkl2XqrtLO5gd_h7OwDZ983q_G4I5-GRlaCnyyul2NAWacUTl1E_IAQYhHKXnywlBUSRZ7dcO7OTtywJnZ0t79PUEucs1fhSsUN8pqxclGzKy_XMuEHg9qIIA5cB_sdPYselycGOZRA4DHoUHdHUImKOcej91iJbVWFbn-4YI8Uaw8a2wzZhChcPJB5pw2wbLKdQi7ZsVBbV-87XKOQX6z4B9SKuzfBE98WVoPQqgfudZ1qjOXnqUbxgEtJD2riSxsVzMirhM8nPQrVD36taNTjpqYi6dIVvGjcP_qVV7liAzA2HzcZ7bDLJ30YfLpo1H7-oopbmwqJGzfrgEpQF9ncQGIO5H1hrOg1ZEJX28ebHV_GlEu85_jynZUlPYgVavxOQ8AzuGd939l7yKJQAwURD6B0YMSuVGUyCHsRdcxsRqBR3WK-uHF63c3SqmfRfcFlyt2kyCqTMCTrV2saOe6_CElsXNAVM8qlHu33FL-0FQzAuHMuaJiZU69y5gh355AV6NQN-OQfMUS-UqS-A0e2BXUHbBy5RFRtdDv56BvzHkLjyB3KJTH2-k_gVUAjYAkB8jzdsGpcIhkQ6XG0Y0YqeyvtGJVz1k2ebo3KNRdzVbVsvWpH3bGG7lUcHNp3hoXmOzGr6Oco8&prev=RQABBB60CA98458C&p=4&pg=39)

* Intellectual Capital Resources
* Nijmegen
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/b327eaa30248f96d?ql=q&sig=12828d384fdd8ac24ed0900e684b7c60072007dc&e=PtEeBa5tQVc2mSIrXRLJMUeo2TuCxBM4ZFE6MVWS2L5MkHHKgMRyvlOkHcRyF079CQbo_X-VfIf6S1fOvgEKJ0v-FZOkgp6ki2M1LeFaFLJ40NQGuwd9FDeExxFjIbFk8sY61k3smJOzrcxbcO5GmegKUVB5ylfGqGVsou2a9xG0W7gGcfOgegRMCSYy_i2XdW_d_pssZ9O9wC9nPMLJxZDa_dYPCAd05tujgzAXINQ153Vkvz-bt6tMtaUUZ4-wsF7d1UAZKPo-GeQfY3nr7OYHFjKAEWBjsqZo04MMKHONW2JgcEG9zTkPFmqp8ogyJJ24v7twip9l6z4MUoKAhMCukKvKeDDThQY20WYjSGX1QOfeQFj16f1DPHQ8v39A-55RPZIqErQx9ROQX_aUda04Z2vAM3x5BDiSYqEBYVy5iik2w_HXPsu2iYSH4AWnPHPH9G78Vx1J_gDncQWu3z0-CbucG_7KKEMIfyF6D-iw6QOuGec61__Fw4GXabBoE0t0q1UqRDZv252eYcfvA80uMBqhU26i3qP6N-xxuN24TyATD7qUJ0LqsLuWIyJp4PIbXUaVgcVU9C-9yxJK2B8vnveZE6gR2Fa1jXGoiOos8NrGN-DuW0ANynlGX2REQlajY4j9vqXu7IRKgsvqZ3Tu8reQO1u1h5kp4HT9aBbbWimENsinrrsWD3rD7BaCB63JeKuOqEw_DMTP3zd_57f52lIEyRFJGB53Pgb5MKnu-vQekOtamoVGHdC1aBhpf8iGsOKRYLnj0wyu_Qq7PEVGkYKLoF8rQqjeuJ_KO3jiyodv1xTC-Havu6ymkpOviB1yelUCXlGllvAu2qzC3YssVT_zSCbbZPVKhALN4rO5mg33lz0qqKQtjVQ2ZqRJKc-bgdIlCTcKTmkX6t6-9d6NhpNxf8It0ZU97-uC0yf7pT3NDTSW1lhydpf7_X4OulLu_-UOAWm4eAglgXKLLq4GLUCV6D2A-NJSr73Z_831PI3dG_MunTB2QQhgc7nD-Y0K4J3OaWCC3GBstlhfrTUNmFEOOhSisYg1x5Fe0DtjvOZ_grPU5KD-XdLrciRc23QrR_ye8Oepir_3kwmShRMkH_5SGtgux2fHeVkFKxE07Em1rZeGYt97Ci9Nb8vqh_Zfa3Zh1a2CaNWFAG1PcmWhCoA83p0lGUflqPpFkfG4V6KAnT2QGCeZ9X5hIOeu1I0MXIr3TKNzWen7kakvn9AMCZCmokP7wWNCJ7BWWr1v57zSulk8Keh2GrflzRcFOXMhjCo8RZcV6NCKb1Mggi8QSuSAnKUdzYfiWfZyf2lNigGvh2FdQc0EgqPe7sh89UKiSWVWoVU&prev=RQABBB60CA98458C&p=5&pg=39)

* Intellectual Capital Resources
* Almere
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/88ea42cd57b36d43?ql=q&sig=f7f3d479a3d75b4e6680461a387b8a4f54a394ed&e=W6khuo6UgsjdCSZuTndkFswg9xkbAgeIXLXCQPSyobCVBDErwE4AB3NZbRvVe8L2kCKm22rGl6Ainkw07CVAdKnisNAsW88FfVJA1Nl2lVyplTTjxVxQvcmR3lCRAaIEbd19avgIq_BLavNF4lMDpXhmvrEPBclN0WlGvt1sRwuf5c6__KqPEybTcB2pVAxx_HJiAacby3vrdvkMZGvxcc8ba6mj6Hk9ba2FWDOG2hNIl1fWCIGcDULnVbOx7r7EHL3_1unlYDc95xBOLR_jbQMc5W_griIOzu6Jk2OBD6rJKfN9T8fyjZ0-UxCiJpXsTzMkMW4UW5cb5kdJwmcK1ofHk97m42cNisn3n6hRWGfFExVH1c3YQOtkuz6nKIOAC8bYRNg_RwSq7csEoT5ccs8cU03cV3Dv4tV86t7xvJSiGXWqZQxr6It0G0Dzu2KqrEktdLvEeCSSuj148cwalsG-XGx5M7YrDeo7gD2PpPEhxZpFtu9VuBshZ2_cCnP-UhdFFMcINdBmdcRJl-vWkI5b20sXB5Q4be1XN1R7cL1dgoPFdwBc9k0k5mPQu7Pc-sJtl8XzPo-RGZC0qK7qAp7pM95AUvrmYrEiEtwtOfe1fDvwyzCJu-kxW4ioq9oHtfS64C2vDwVt4nlpaIhBf9YRxJ-mE2HrcMrSrBpFr_eU4RylIODXlVZmqexbklI0TOvEVEWEZ9VaZxOb_MtK0Pidwlg5Xxb-C47VlxE7ERTR0Io_SNHPzurMF_O1S5uh89nxUR-1p_HQ4V5jfwFecLFH5MTYNtN4hT0_yOXc7z6zUXvpfpI16HPm9FDPE3xUU12Y_84xUqfWIy8u0eMkEUHjUtxChSNpSDbTqDiaInrp-xABG_IGt6mOYWxIhiRuArcFDETSS1bfWdwmqfg7AbhIz1s8DoRyHANl_HLVWyrJLyuxqsZOUl83J6ORz3UvCeK11wXsOo4bK7Wf5dTn0qbQLrn-uuVL79DBi0a9sx4GQTkz7lOnCcryUML4tOrb0b0j0mfP9_R4Ym-FH_iVKVdLwe5ThDlFcjESP31A3yjxajxFrae35AJHPde_0TP74gjltPHr726sLhMiF55noWXpa1BktYnX6_hn_1wO5OkCd90uOCXq4kITSG-WUz3BWrebB81TFi1gnf_XERhC1e_qrv2C8Gur-ntLRpBmpl4e7Z2mF4BYlHW2sw5KtR9dWiaf-a6nVGx2TyohCOIkbe1GbouNvEA9HPuBCuLRBAul0cdNp_cCTKwhj0vkUpt5xUPFm-kXjqtAIFb2Kxy3KXE-C9vCNYKLNFr39_nYIwbDK6laL-HsyfNwTWQqsOxbZd-o16ZM9qE4fOXO&prev=RQABBB60CA98458C&p=6&pg=39)

* Intellectual Capital Resources
* Arnhem
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/5c02895a778bc889?ql=q&sig=a6c93a472eed32fc91aa9bb92e6ebec2f7d9d4df&e=LuYH6kyvl234X1-7JkWNGwmDdrb3GNMKqUiLivtdhgFH7_19dlE-PCTUFPlZf7y7NjlZFNeI3nI_xINcavzoE641XpGkan8jlnNYA4L0xF5ioh1DiZifHaACtenzQTl9Gek63av_UxD088DHNtJXyqANxLV911hbWvfuiodGYvzBYTedQCGMHeyVzkw1Nm2C6O-xwH-ErWrerWpsqeFmVRi9GWpbr6EO4i0Q5lNSlzLeScFYPPs_AGs7RiUGPBMieFL2mceaUUABxdqct3jiM37KRWB-jEnqTsBMt1kAG3a7Bz5yakNKfN2wAZuWqJCRviPnRUz5DOpjXNhn0zTfUpKCxy2TTl3w2Co4fW29PaDPJRJC95T0UD9GB-4Sq8d2G0zVQK29k95XUwRtOwV0QsKwBYSaHIoz5VxaWZT77TjNZnBNw6jT9IDV_sfyCWFlAHLFlywmgQPoryttnjXT6TmgTJmrqvWu7dNbUHBpYtQDWXs-BOapfsdbiMdxa9s63u-WZdrTVUe1hj49WoP3PtHlXwaihprjOM-TdZx2ecc7i5C_2p365pEsD4oxjSpjXmMzCs0BWISwpa6WMHwGd25-1v0IZq0Eq6QU8XEOLNGh_oGBpW9ReCsfusRJ2KpU2mUvGS1Tqxj4a_cHy5GLCLpVFtcRP6Y7EdCdARJFrmjld8KVtmBHtqgdLPsNX_X0RVHCbTbHHljSlwk3gPLOUl1PVqrYArUxRveY2N8uBNkmzwmvoEK0_saq-z8XnDt6BnG4dBTpBp0squAFM7UOk6uLsjqOlEC5KZLCf2pgX4eydfGwJiWX_z2rZ-b-LHbDWOKU_aaEhI_LOpGK1HLi0EZJ8X2ShcqDkf_-3rlRhX6J8vkUpBZa6jGDEDhlu7l-5scxiNsAIFaXYyGD47_JLDoB-FOVLA0IAeK0HZZ_Uw1A0Dof-Y3Ku2NtwuMU6DxC6148vEY_fjtcLfIyI5DiiwyWQEnGomSn_FlzCtfdLYNoZqyFEWQUUx1Nsj4n0gICS7NB89_5Ppfu2TA2r_Sal7rVd-6kbrTB2bvgW9OmVlNuIuK17owioQ3npCVvyIAev-5ekOoCiu_mtM9TWVwGTwc2jp7tkyWfqMWanBBiXr4qz2lWL6Xp4TDpz5CTDIWntpu0Dg30HZmcZIaEQLie8dgmeg12MOdAur_16vDQB6ZAMxPOztaBb-YQhfbjZiy_a_DUmUh8C8naKdQN3Xs6KCOxVCqHCy1nBqiUV2OeIUkSSnUge3Ak1pDNhqnUYlIOjUDH0NnsQx2JMo3W8sUpQGYQ32ne7hLyGNzP3eqZQwKNMxsO9UPNpBwL9xYqXtcb3mq1LJe5e-8&prev=RQABBB60CA98458C&p=7&pg=39)

* Intellectual Capital Resources
* Amersfoort
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/3bca86d51aeba479?ql=q&sig=b35e61823215a9f33f55773d4a9def64641a38c8&e=09AMjvVJSMu9rIS1iqzwNYpoqpnNVcJhI024gLvXF_ruWHjGYut3rZnx81ar2tP76yzn9MV51AmYTLL052ngPhzZtMlLNsOtZ78Ovohb5GuHPGtzKPhBxiInMJPodpbjEkAxRrMpzCwvOo_pEJ-ITIPNWbyhYToo0rpCuZ9hki8yzYMc6xJ6TxJlf4Gz4EIxwO5JDJzSvYTtW-D2DLIoh5XOe-Jos_k-QHTl2ARwPd_V8Hoe5lOsLtJ72o_bTd4gb0wkqglcLVdguRcYeIuiBA1xFCv_zSsvIj1SYLkRZjQX_fF7okwZja6V3XqkyfEnEmIA4Jh8gQCHd3PXZgLOgkAmMcdoriLyj3PrPsb7QuOZj_vNWO0FI8MD4h_Gmp-bpgeAcSo_Ew3OXOHXNKIue-FrI_Jx3BNTorxYRKEr3iht6ajU1FJqOa3wRFmJlnO-4HRm9rXGWX--S5kgRLQr0FQHIUQgK4rdgyZaHAqD0VHXpYE5CJrTolF49vfXCVDYDX_9rWSVUxdQ3W5jA91dx-bLnhSDcT7y1jJ2r_wBOZ5JjEgpkvNEd6G1U3OtvC6qensduaaECAwAhiW69PQ-33Gvgwu68v33Z1kMxj4rLHJzM5UY6E9JnQmXF1GH3uQLcrnFtpmKLpir6NfE3arWL-a_r50mYjq1DEvIXr48fkcCDn_dAACyJ4wqkqjQdaAKzQTlvj26hSIE4-HEQjrHmiA0iSoKMDcajsiu5n9JNGkTEFhZZqAUPU7Bjx02DF_XcNH4aGCT-8Hq5XaLsrNa1WCmFceucldBCvk6op7mDoJzTLLa7IeQJ1FiFOeC9awd9Xa_WTVK7glvAezZAM0jLYRk7r-uRiQPwr3pSYlHJ4iXHXS9hJtDqSw8ct8IbEQH4zLttZ1-HFLquHse8qNL3-iZ2OUeUmrahqHr9-8bo_R-MHailTq5zkC_sJSD1lgmo3Sx0VTZIGrpgrlWqYfqWZ3tCsHmvkVZA3R5bYjqhMaUYt8RwIcdiWwGe0poZDH3BX7tMq5V8ch24JfoaGItNZWtqDNe2hLn3K6HK0zq5NN6AinqXtgT9zHSX_Gs7XDbB2XhnAG0STefCVRCMxKqu2eBl6j2jC41LI7nj8-JC4NCMmBtaAagat1kA64NVm9VE_2Rg0RDbEFiWalzJQSvLcU0KjlGg01sCtdyz6nbuj4hiUHEMu8OZCtSljMr1PTDWqs4v2DghLNjDvbYvBIDTJIUwqTPDObqYJAKcEgBvl1yjhZm6SDGC8McAsdQlVipawZO3bg-YyTjs5Rknq1pBnK8je2YPgL1unxsGsz3FdX0F_9P5FrNvwzY47jqGx509kKb3IToWTA&prev=RQABBB60CA98458C&p=8&pg=39)

* Intellectual Capital Resources
* Tilburg
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/4721a0975794d53e?ql=q&sig=c8aaa2ed67779e95998347107eef702cd0c5e330&e=5JSIiKy_IZ-Kx5qzDz1IBJkEtfFuPFhXSfrQrqR_G9iTI7gjldd2QHTToTFz6hFY7GPUwWIJevjJFz7iTWm7MJ_L76IcAbHmGtMhKdVXmViI9I_PBD-hGzmlEYQg5vbSpNaN2ORMgpLxUefc9MK8Gq_QEQrSC-TeQc-xv3HbpIeChCRsJ884ehtzTz6SeNe55-EEdxCoYMymqGaocDbPRTE3bHLwo15xfQ8lH8SoGyG9vyDfWXoQ_8HSEzRYk4vY95RofUx5I16MCFKYd21iCFixREVz8sX1gxLl_5Zqxmm7uxd2e9eF0WxUWO-tsa7g2HoV_Vekpccs3xXw6EbNoWxxX5bUWFNuxjkBz5haZVrn05GA-omo7ztEZ39ogRhc8MyYrnCH7fZjykg_aFiTpVlJ34IZmT9hxnYSLvf9dNrYs-0TGl4j9wjcPqY-vYs9svWEUMcd24Jg5_ekCEOr-0jX9pk_54fQ_0nR4U3gupTzRpCN-TdTP5QkPffYf8XCU2gCEfn-WT2i5m9K8ZiagJVy6FVfIUCTWJxdpLnWDfJ5pkjrbzTlufyABKsNKVgtIMFU7VaGZ-DNbUyB46u4MTn0Wh8st0dDPlfl8wpqxcr8iRdzaUcpYrfezD8YeCs1_eK6Di7_OVm2jYkAHVQEgSUGwxZ8r75AniTO4BsTJYLVOI4Ukz7fVbxcRuH9B_4oq1uqx7EHKUcLnKxFY2LxvIa8af-8H2o0hhD8ZuaoQlnTZybapZim5cYXifQRKj04YhYNQUqsrdLyJrLIbN9juiqPB-VuCKTzOg5sonLRuTNd4txpE_wqc7KmXGYaN3J8nEXGYKuRq-YDJ3n74wG-vkXR1J3z5KSVcKSneJggEPWHJtH9YXYNpydz5-JW_6P8qx2KWznxHEWYWz2W_t2IhhqZDQvlFOTLEV50FTWWq3GPvChk6OheSVTkofv28-endmqmTPXxU6xzr8u2o4QTM-lyagQbwbAjvimpfE-ebJDPbNaF4ewcpKmL7UZglyw9NFck8k5o3PvDsfXMV1fddoiLA-Ns2bK8JyeJu5TQcO8fjlPEqD3X4nSgITKOG8kte_og3KBJY5rjSaUtSn9IUDAJ1z6fKvBChXAKP2SrMngV0gg6IJR_bo40tEPgFGyNolUZ6sWo_ADB_Q4Zjk4fj-iskPN4oxZ_a4oBBeVZrm2gn-3Ou8mD_yGzN-xn0sk66-kJZ-spkGd78574RO8xd1Kq_7EX-k_JOgLgL3Gx9Xtl-3_5lySE4WlL9R5Jkrp8w9w20ilzZ1SHXMlTligsr4dtQjNi947fqb8hFnXnPwG-D8i-9taTkeZnc1mAsRe1-DAGwpq9Vsk&prev=RQABBB60CA98458C&p=9&pg=39)

* Intellectual Capital Resources
* Apeldoorn
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/4fe13741dc9cbca9?ql=q&sig=de8ba3c2b637dadf0ae072ecdbfc8abe375d9c51&e=Umz7Icv1B81Ii9btDG85b_bafJBevMrLqcebVyDIAinjUXzw56KgY3WHR0rmCcstg9fW6ojT5QQ5UG9EUqLXsgILhBFvkKLQtBdzLBPyBHdkxAJbHyydflxw9a3CtC9BiwG7QV5B0yjrO49YkO7HqfuWWA9-B6H0k4FLHOI5PnU4Y4Uv6Gd3bt_5ly57Sf4zfXz38SvUs4UZtPTvJ0pF8OnsmTl2cb5Jx7lL1PSlFoeqvN40AlyOjLPYC5EcQUg4lmAd3FpmYT9VOtAqhvcEMlFa4G4WGhpf_0jfOwUGPQRffpkfaXTpOp6FOGG5e6AB_x4lo8yWNKx8Jwpkl-PBYq9omnrq1lYlWTaF5LyAQQ50MWT43HEXc9YB8d9Vo9alCshoWPb9nBmFSSdJlmhy4WbifRsRCmnqJRiHrcsL1qpxszgbVBmfRglh_E2rTF_FNz3j7QNBjZjztbkmJKVOPutV5OJhJsEK2v9x4baEj293RpnpJojK4UliT3T_PSclYYyCh6T_H10kx0Xz7xbwgKLXQVfmKcy-98QFiCx7y0h_pf44meJGl7z6Bs7HmJErMW-Z_KSb0MltBnHR7DCKTqQR0yjI3itOFEH4V4kbhNE66BB40rTNfM-lr56le0SR4JCS3B-bcv3fkvejcEwGUDwHY3ej-IMsLVt7i8BOH9kOJ3_kzVtXuK3uWvbX1DUjMe4N1QzeJl0VxlEH8ztiXRPFy7ujckT-K4CmukeCd2Erl2bRQKziSLmFMu6L25BKuxSc8sbm-1ags02_6zkl0_k5aJbTDAYjcmW50g53E-4UIawFgMj2tGsZYkNO0e3ALcdDWu_AHH9JEOGzf12En_uzFG8rSe8q0AQzFiN9f-sEbcZcFa8xtsJHz3uoDUjX_98AlvGS8On5k0pzcUdlAFV-RKLJtH9HS_vYdbeTPNtFnYTRuZfx5GrW_Xewq_QT9CmSQ83Nf99ZyZHWSaWZUfehTKLp9jdaStQLTTD8mfXLP05G6zoB_LjlceFhI-vLkexudI2E6Pkz9l0TEUY06_jGiX0c0cbcnGwS_tFDVcDzMwlmgMgA_rWBAnc5R0sEPjPn3ikE_Dndy0uAh1ifL2DV3LKARav4kfzcyDA1nRDr11BQWBqVtLDVee1X0dbT1dXVFNT8IGSdXm7ugqDcY9Sczg5i8hwXS_I13g9KW0PIeo8eRrCzGOof71oWMR4O_Hk5W-xFMelDmzgLGlEbQ6WMMc5qIExWeF7tBgSIH_r-7M7EkkiLkCMrsCmizo5H4j8pVT2AV0gBY_x5wZ7Sn8C4f2FKkmnYjutpixVsTqcPSlenEvRFNpKx3HxjW7KGwirD46b9QbPxcVQr&prev=RQABBB60CA98458C&p=10&pg=39)

* Intellectual Capital Resources
* 's-Hertogenbosch
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/e7158b8bc683017d?ql=q&sig=7703f945e23a706cabfc11c74e5644d442c611d8&e=dyKNwo47xKsHCrvdjrDiI78ugPf0hAMTG-sT9OCPjUlrdH_s4k9ew5jkPHLZi2mkIqjoxMa_K56FPChG6mXJoOg_8Xe6NM_0Z-bRLBAaSCfme8KPQdX1QZBDnEH5xCpm3tKpbcfoQDncqUrkjOvCeO99WcqWIdm_Jl2Rgmu_-rvoVVUoDzPpNSiXBJmyiad_ZI4VZMJBvA7lZEUPXcmRlL3iwVSzrfamDUuDqTRlLr3hQbe6aGQPEDEUqTXyUOH-eoapjfbmvDEHHVA60eDYzHR4f-67nS94u0xW22k147PXKfa0dtI_5emUHh2t3NusesYZdnpkdyZDp_Ogd_SkT5MX4mIS5OUMhUVJzWWcFrr9aHxQca6wFFv3KCpSmnMx2ZPwg7QV0B2XnCOvVWsHIUyLUHfgGxVtj9uSgz1oBEUE5mCxO9w3s2-_Xl-UjMLx6c851QT2BjfIyLGOFZoR2Jbf1wJ_3lgqb3y5Lnn5w72nWv2q2m0FA-Bqyy87c4EOOL-mzPK94fEEnMOugPCvuK2sfCBJ1rBcvSmYEZon2NFM7c--vIuBhIJsWoX8NeHtKIHa9QsLNpYriYLhVpJWZgzwYLyw84l3e9sAliSRHSwEYpdvNTno8QpbNYL_wdLWQeMVbgbGBJsYm_-dIcmM4Mxy9SSsusIEZWwoHwk3m5M6CzEyIvO6WMu5dTBw8mI3L30ZqSwG6o5ajZjIt8diOGR6KdrszpUlLcWx3W053NHz0DdsZ5KCbyvfnlhKQamN4THU8GrcFlalLx8d7VOzuugvv27Fn9UhyGfgSU3jgG11ur3pL5PjSAAGlHfNUjCuA9uyYca4cqt51LBriqKFu0sv-YAXfvzxGcB7ty9YNL4f4xwLVQbLENW4TztsthZ48M6PeUWMO6n95Uqhwh1EaDXRliTQgX7-sUOOGydGwrhbdM0Blug_YHUYAEcbAlw_XEfjqMlnSlsq31LTG0bEHuA3EyD8JKtCiluReLNUVVTzVA7O84ooycg3MumyqRIuWZIG82JFc7g8dMZGkPp58XfjzvX8L6GMs6vMtuebJnKUy5HX5wszH4pbEM98fo6RRIvVJSp2XxHu0h8-O11bOBaDN0zZTMddFJuUfLk6WgSHJt8RF5I0tOCNlNhL00xliuAQlJIPMNBWW84YDXbjUr_XvAOvOiPhfILHyJxYOh5gFasL4XfEUpoxpccqBnlm-3KT6Wa99WM-eVvpt6gqmO12r6-xzyIVdKs4arJagwuJG_ZfZBtgAYTZj6GDpTpOKmCoHZHYUj5abunOyw9keAO2yVUsEd58xmJX0GdUppwrA6liVLp06C1Hs_lPzP-wQzUyUlNL-TuRJ_Ov&prev=RQABBB60CA98458C&p=11&pg=39)

* Intellectual Capital Resources
* Zwolle
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/035cc7e6b8552826?ql=q&sig=8575784132941f6c796d5de7a0a711d4e00ce9f1&e=x0jUlAkn5kzK5jz0LeFh35gb4w85oxUYXAbj7dHWWKU7TTF0h_IlzqNVkOH1BT4E70EWNS9VcMRDfjPhtlfp995g7AtjSBwHlP-am_UeEP1r6wd6Uc2r8E6gIH5cFXmNoXnY7T_5Xl34Nraj7pjzVLvyl80rMTim0917D4ZxGhxIdwx-7dVtED2PIQ3JxsePNcRA4a29lc1X2p_Fw_V832RIEQN6WVAU1NJSrcMP9VQLJPjcGT8uZXV3Si6buu7dE8dCeagL3Svzq5kfdM1SeqU481M2ISHNRQGGO0JayVcYgzf8maU002f8l1MIXCO6I2Oaff2xrsYFKElynu0yIxk6KjOBEMfSx3sCQxPNTKHFZsq9oLlJu4gjuqsFQ5rugNd_EhGqMAYPuG6uDecgdM5aeq6AsSbdLkolVd2fhPlM7GQXmc_UArT-RSv_uBEYX73b9nMSdReQXQOxGVg2M7fS5zl2LGlZvZ0rGI2bTfTOaA5RZ1Agc5hetcc3CN7C_RhUFIRXd4cpD4ROdHaD4l5KgrwpAcqSEu0DPm_Ukdk_JaH0J6-Iu8Bx3vOBpv3Mp45fonLsmwizie823StnH_Nld8T8XP2HMSy-llUeS-uDz_ODeA9I9odNlL-kVcOQD4IOEIsch2Fe4m_6cGPSP9_g_5VgIx-0sRQLuKF7KVKIbEcoKkbOoUevVJOIvNMzl3MRO6EYi6vd8jam-sF3_9aIq0_kruiaYp5Nx7A0yIr0AvuzKKEfu08U5Yo62iT3XBU8cDHrko0aVChrNlwwrD0UCpfLmA2IQnsKf-tnBxMU3rIIauF93xnzB4fbGtpxQcYWsP0Jd3thGpoepBq22r3ha9gRJ4Xe1wbjyMj6VKLT72R8pXSj2WHbiZlRuSlyJBXjynnXq4rYW_ey7n_Z-u0E_xmt7JUeuY9UQQTvmw3zYnpeV-g0bEHLVsoXI4fL6_drwXSxp6qqGQxvoMRpnk2QAlkrl3ECdKKkew4D3VhRt2t2j84ppxZewas2kXphppDJjw55z6Toz4biIglakZ5bn-0YT0Elp8BjkXeTynSypJUt_3H-Eqg9vz4PAV2klR-flNxoS9JsV--UXtGuRFZWmf5b_AicxawGGBSowa_yeiX9DxQTtbipyDjKn1axUDhBt32PR3-dpjFeMnPOrhatrr-Z-vIRjxhbCr6G4mD8yJbmFsIiS1F4CXk1IZ24r01-XNDbue17o1IjvieaNHbjY49SwlSREttNGXdIhfvXyXTsOAxryfdF67AIR5Q6ibwR5TXkoOvcJccTGiYc1Gz6aOQbp0nsl5wV9qFQqkqMnUK5lHwFjuKpI7ve78Qd_Shdi14q7FM&prev=RQABBB60CA98458C&p=12&pg=39)

* Intellectual Capital Resources
* Breda
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/9c72b77de89abe57?ql=q&sig=26d8f3ee711fdd4edc5dda28b55a4826195b4b56&e=6eWms1nqrFDCstkwtm6B8EuN4SsdXqf-1Xn5RX1vUJINUn7I6NI43f5dTFflgFgTh5_ahZrGXZGobbcsh9A5HvO7FRAcL64gEBqqoSm3yFZ9Kxu67m7IdMd-1C8T4u4vsthHbkDz42QgiPvVckYXU8V76GNnTSQWb6NhKth9Q05VUlqbHNn1NLjJULPVxtKAZ1QaNsTJsrhA4TDVxvB7b8M8A-9Iity8fpj7NYmMWYMOvpFPUBDWXmDRvIvzJb_fJ0ig-alLqZliDZFAyNgHgTadM2TW4ehZwT8flUPugX9dj9mcunUgJsBJ4ULPBYk4Gi-GkjEiRoEGn6ZPMDyYLvkIvDCRDcu-p95k2ZqsTc95qjPZAblzOxpWMlFf8HNkwEntiGa1E56u8r_cAFco9HXcpHU2lZqkvKU7aAn9ysVy7TP7IllOr1qFVxjfUKx3zmtIrqHIhLUppJ8PKVxC5AqhVkPfcxX6XG7UHoqDwvWtdemaB_dAXKNhbsKCRnMyrYWmD9pjJSRN0KH9MHm74QCylcaaWXAa6Q27T2vYlYoARdcsawce6o37c3vVjEH7PaXOxyEij5LgEC0J8DQiM-DPwwxCf7_D26Fq6oNF1Ud308_BNwVm3_M1exq5r53IyAA1ApIE95EI5Wrb5yzjj9H6ggV_kox55g18Krxi4IbhlBBrLmFQVZiw1invG9YnOrkF3plXbKbcMilynEM0IBUV8xPUEHIFNAr_Xy1Xk7vUaAp-SY1Qpp6hgZV3ePcRdYRivGzvpAv-gpIap9eCyGGfGy4MF22_uekWFbqYnNWxQ3tP4NGLaS0ftiOsEd1cg9RRgQEztTEXWFEUpfsIJohzLBSOfSc0XSqbnW-f7BQwPrSU9l-mFfgM6zSTa9l-ghgUE1q3tumMcmnm2ZFpb3G1HOwgM2u8y3WLbY7Jh3tkUTWBMAxx-VV2ZFVC_6LaHp3cGSGlQf11oJFLlZsK9j-Rzcdx_m5qZeUmdJ8qf63UktO3-F2qQPLPiOEKPc-eFlnbzmqqUU1f65fEGhIXHRFhGH46SvcSIZmhoxGzOElC00A79boo47GQkZRN0GApmHc7z6o-d_y2Xiq-ujhDeK-3ZA54rw6vMUtfR30dIglIM4u0ZQliTfJGGvKm7zmx5_F9zzrY2RLB24uSQhXIP6f_vU8rQIir1m1TIYALCyepEaoeff_tJVxJHaum5G5GeomBTpzTVGOODsMB2dolGCpwaWERk8AuEIg8omBPweNJt8Xq4mmsMr9Bwr7Z1FNs39YZv897E6nf8SUJXpje2mOp6MqAg5aoGoxf5eus8DhwGaPS8kyfsuZdIN_GL8Qj_utPtEeUy1U&prev=RQABBB60CA98458C&p=13&pg=39)

* Intellectual Capital Resources
* Den Haag
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/7f997ab6e8d6c6da?ql=q&sig=2e1f83d14a3b499f45adb1168da9329201c434f1&e=T_MA1cIRJ4G6qWrFcnV1x5XpOdkcHChh4sZoTK61erCNNH51O51aZofvRCM5DL_1ZCWokebb1T3sASDobuJdM-Wq3HcbOrJ-mfJQn_8E_hMVSEicOPH2gSVxTMblVehBLsxlRMQhhTQevc6RYE9kRM9gfeszHGiJCdGD3EJKMbYCvDAgYzXMDxdVaXXT44tTDA3ed0o2ApSquEzlylHQtGSSVR0jU8mBNUFE_w7ixWYoqAm0xd0LSw7QdioO7YwRjaAkB8uhcJVQ9qa65kx_bH8EWpXs2T40kyqODvAHLDt6LyB6y7i9CMHCJFgB2OSc5tXRoCUrJBf3Ss55eW-0cyCJ0Aq6XWiArJ-eZT_r3YAi1u6zc2a4idZb9Mx5FXC_-GByzrUd5mgOl4DVoVS2S51LIBfYmyi43m-eIz5gJW--HYd49JYn7fP-VODBDJUodzQYu_RbbvcZZ-d9SxwZsbzGepNMeZCMJXagGNvyoVq7-ZFGJwoUbIWc6yEscQuCOomuIaz1a_A8mG7vZCc2ePPdDq0fiChUopItjZhqnkT6jYuEx87rOzI1ks6DJ7ufQMWBHpL07MJ4IJUbS5LEGzBt1kJsmxij1aWWehNFivJgUM3kmc1LQewrx36Ym14ZTdnKx5lQfX1TJlmvt7zhZE2xcLamWA6QYUVJan4xW6gYG2i7uLAw5C8tm40ZpabNbnBY4bvgsftgPy7ohXn3Ep1AWtRgleI-uJ20ep7q03ncxz8alvJ5XC-C76hKZuOSLmx4TGBimlGtMAnxnN7h-8YxeD4QEmGoFPdyaXhJIBIDadyQ_HajaPKNdugYdRTvbaY9Sb-OIaStKEyT4e4iQXxpPiaYjXkVjrxiIOTHYY2jLR8qhTa8w4j2Uqvv4u3Uoci53P8Is92qtRt18nQIMeSJrtO-GR9GAPI8ZaAXBH0R_x2SReLZlUAJLwWx_Sl5aB84ELZZdTvAagEIFzGSlNtnBLXYbwEDmmwMdBJs1_6-m84Bdtd8RXTyftmOMFuucZ66-noC7Lcyt7DvGBvhRALyjanMZVnImZFARgc3C3dYSZDPEiYifoMofY0asir9OnB8p7pQQeja63FBcxxnbUJEnN-tEjX-6O_K74D7zlumQjL-NKuEszJ6ByvQyIWdEa6wDToMbk4cBqgL35tbi1Vb3CC2SPstwPDkB3MU5yE1jBglCxLsK_XHqA9yFZJne7PzapcqdFBOCRzg4WB1M9jgmFQJ0whRBCnbHsvSVe2W9VwwlmCYtO-ecJLX8ZQRSsCppGqVYvBO-_wSQspxvFG_u2DT6ewgRfajrWk8xl_5t4RQGbzCMXm7DNg0uXdgTQkzAz_gcQfIeQ&prev=RQABBB60CA98458C&p=14&pg=39)

* Intellectual Capital Resources
* Eindhoven
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/d39718f40467b2bc?ql=q&sig=5377ca90abab70922f56c6c7021d91656c1a5ffc&e=Qies4M2seX6dY0FcLMVykqQzIwFRx6GYgYOoPQpg3-bEDsEeY1VjVVFqqsWd9qBcu0CSzACmKndhQw2ebZnDJs2eMk-A2nq0pwu7sipKzlIBNllWvHiUDd8Vpqlf_rv3lwWrWQpxCuRgVTAWInDbwqtRjWMTyJxFat6wwXj9jTb6kPuL4pSiMjtUBOM2u6JplEZqpktmvJhDJC73DVBrDYkzMeQOpi_smj-dB8322IkM-QKYtZ0JacmKzQKTikUMxwCENqzzop7_pXWtGAo4OkdjmA5WtiYhOtpSQSRQe7o8truU0uMx9rY1dQ2Ff1fAL_Oq51SUgHVQ_i1j2ebqEkDLx-Yzjslnip2U3hWZKpUq_ZTaLMuxayaUwmO1tdAlxKWw34wkJfuXy3JjISFUSR0kVfR2nyGwXEJyV06WuSX-wf7MiMTIeJGtxbG7mUuXHamx-RF224sxhHskwPmnd8L3coueuNor3CdY6bYdcqy7uhucbACezSaFMSQ8WWohKf9Byrh2Y6K51cYIR60vD0ebbhNHTCAa9uUKh06NdpzWUYTLdBDAkiYzHPRvY97djqBYV0VR7LiW5FaVFP8dMryA4qfgPQu3kblXNnYiq5IT1S8nfQkAWxHBxrRwL7ga6SC0GBfi2G56S3pH9iIPcex8PE1mqFSNsVLFtwNqbpax0oQIp4OWoyUHgzSYbq5cw5mfDsFb6m6NVSw9Rdg1j9-4DywpKg1JkOJvJpd88lCiH7D2JfLruuhL5aF095yYd79BMdxq3WrndZxvdIxeRnKjhooQ78Oduw0-GLCFXynwC5dz9IlWpSzyxueHhcB3r6X0TG3NOpWoCsx9H6u3HGM1u5VoK23UFHq3vBEj05oevbMEqaavAcg_QlC1v3026y5eY37h-IkN5zEuTVGmyR9Vu-UI-LmCjzBkO22NHRBmTW-_Uq0TuOwAMVZFa3k4MhcHc0JRUGdLyu5zr_pW1h-YlNfZKaqvgWph_liEd3R7Ohucm66Xcx_8jnDfvL5ZOaNe4X6sRWkJceN9oYnqkE48BFdTCKFPZauA4oWdwVe9-wJt_X0auMsfskz2QHrTH-QSMyyhFo6FOGV9XiZvtmurB6Sl4qbTCiXplxSprbFgHfJY5Abc1yoNiS9Zzyf_vdgrXdz1ISPE3_IazKuDRNn_15eP5qvqeKJ_RfSb-0phl0KiUpXe99zlEYuL_fDa1D8Ui0d1vYmhmMAZitEBU_4hYV_dIjFAYPQipbRZsF7s8r1C0OxYovzH9T_Qyw2jfMRS3PkPomULn5vpF3FNk5hLs7LR5KEVgyTWRfaCBXI_IwFqFOx0r_kwiJvOaRN13rE_Hm_iD9c&prev=RQABBB60CA98458C&p=15&pg=39)

* Intellectual Capital Resources
* Rotterdam
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/64ea64cfaf666e04?ql=q&sig=36f501a871bc2cfe0dbbae689379f36da4172c65&e=znVDOG069-sTaikeOJ8fp1Ny6XUazuZDA9ZSBcbvcXPTdNansii8uhtBzMJJ8uC6oXjbRl2Z3dInrDMVHr04YZJU3UlDsGmhMP22RwD0ROXYFfdEkVec76M2TrBeEmMxxQwd8I6uXr__r7CWy3-ZGhSW1yEP70oehCqCdaINlFGcyQy_QHDmXUFSVY33JldSao61ghOLjaxTR5Gr-AWy5zAmn6QKGdtSFX44VPgUyBlPDbsZoWc_YMMeFT8VkcZnhlqjXY7Qhjt102bjI2pP-hbkfRvCsSqzKeHa6RiLt0bBPEEM4NOJ6L3ogSEvBJG-8sf1MAMoFfd88jOF4h6kzdyvdp09eIoGmzIxWRaaU10-u1lWc2WkqLMZEW3D-yzLDyJSMfR9wfEdrxrgVnTTlNP96pTXC8Pr7kkxcXDGU9hVApb1PqwQsPC6XWdEMBEW3ZpFw_7LTSc5R6cKnVZZXP3qPSkwr27uv3ktvnoKIOXYgHOFVdUeceqXRG8-oZlOL8sGWxsjEZzcHn4mYKnaLCxOzN_x2oKvj1zNIRqtTlNjhGOvfge4o2to52jD_BoybxvyJ6aSbSTnjryFkyjZcIHsuMh5JhRsw4VMxtmAzE4y3omzOMxhfUp5EoTbSmso3suqAIwyiQT-GNdLAF9Ok4tixeYCVUTNNpLpQY7ZvohemNxeUq_u-kuG54YeMfL7fGuVxFS9O3il5Gw19HCvOfnXWxDqKGI1DjFXDIjCY8R1cbyLn4T3FfxzCb5pg8ZHj6qDkUDCt4x2QRA-IqWXFSTVtdk4WSBcXD8pLaWQw8dZRE6clXkTx0k4jdh8ogFFzvBqOkKMqKpLgvo83ojVwi0b5WJoAnqk8ukjwc-tnctZRo3jRtd-YmTcVGRbSnWnx1rUzrghaqzzKrle3NlTGYIIcMuLBOtGgioIAzspwmhcr31ZtaAa4YTkY-lSy6jm1TYqRHTW-XVSaPWxGQz6siR7ODt-XqPfz8d7dPfv22A8x_wTNKxPRH_jvYdxuSX9EJyOPw2nzAaOJxpqGWvT5tXuQipCS1bon4pHyID62u4UIh6TFKGBaXGeFW0tg12W50Hgi9r903N-fpfQMRhUtwSuB_ujxCXoaxUQClfUpVqd9ynYwnq0qzu22eeQcCfnSAaLb0iVMr34q4XFXIe71JKKoEONXUByp6mHhs3BfB4sw78QVontvGVMbxa_dMyKRnf5NCt1rZ3Mw2ADFYLeQQc6E62_OukBdbcl3KsfH88daOQssvqXrT9pKqUVme1Zemy_qjmVd6tVYNpVlb6jhtk51sR3AdZaYOgBPLtZ3FF1llfKed3ILtUq82NvL6j8d2dDWEOyE_a8GA&prev=RQABBB60CA98458C&p=16&pg=39)

* Intellectual Capital Resources
* Utrecht
* October 22

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### FPGA Team Lead](/clickout_alt/3c4c016d4122f661?ql=q&sig=3e98adff2ecbbf59b208b095c75369905c44b94b&e=KvGqQMBlgAKaSlDpCMHj4ksA16c5g5GdS_sX9p4ShHhT7BNN0TH5gjVw9Mgvms_AJjeQL5AF0I7rWtbQ3Y48jEX425Qk4tUy18GSrL36u0anAnj39iTy7s3SdHS6GleU2Z7M02RUyhOxFgzsEcVyhzqOmZp6w9WWMJ38mxBsLJfUJtpDlIk_68W8WCCgXCLwmv3AAhx0h19P-qf1wfStc6_UcakkNuNkuV79kFF8PtCUKM4VwTv5YvWK13HoSyVXMaVlX1VLtwe5k7mTpc0TydAqHizxy-WjAmRKzb98XGV0_AyAOc0asBujHNHLUQe0AI7QoAo2n21Pt_fnX46YE5zJTbWGfYoyL5ZPAwjWDacpkYlz25B2a1-DHFqAxhhYXB8HQfSkcO275K_1-wjc9EJ8-a24f1Eiu9E0x3_PcQedGJVeSnC1qQFwFYgdVzfcCc7jgVWEfAnL1gzCb1S4J27_FlBsOb5NpJ1RUqDV7nc19iYPUCvFkLxwdqqUoGAuLtdDG8ZYh53in4K0cSoBRpmMAN3Hmo9kNW3R_aK3HSqGSxoQ5joQHuDZgL5D4aFbnlFZYaSYZlvlVvY1lWH0-dmoKwGPMwW0MSQXL61CgXREfgQG1gHiFYKXsMZ3G7e5RunuxFCA-nUQxrurOhAuRiXuTWge3VWEiF1odztGE-NiuKhz8pcxDH5FPliCBD5eYizrceB7KjqlNh5IFRDC7dlP3G08r0Nav3JeEmsjua6USlcXK04tjId_9Ei6g93-EzYGMpfBLeqXUd1LkklP_1dnxJ68ogPjXuzZhmT0N73wNeXPSY3k0o6Dg2eYp6M6uS1zndwIAA4_ezWYfeEoWBsRsKxScYBw80WCSA7sNFPxx3NHp2psSCK5SzD5WTyYtt3G0TANneGXF5tIfUnTFkOtG_78fcyXSKHqrNEQlvjNBsdgUpbxM-Xlylx2xj2XwVvoI82C4zVCwJDRQD_XKoJyj7VcbSsZ8ihv_v8X_wSULryxlrU64iplxy_B1l-i9lLspzgAxslvnreruzyFZEJcAV8FeugXVFWsSy6mvGiVRxnY72o3JOKaNRxyHuIOW9nyEZ5pvGm-t57sOBtN_sZuotYjimw0XN_0mrho00Y7LQptZMPKU_ScsaLr2Hv-k4RySMpwfNKPBX0r6RQzOvviID-BLPuGabulwuzQTUELKr6tSNvl63ND6-bjjDnmz9dhzPUrAD8Qx04nAIAYGri_-UVNuqVvlDsh0-p7S8QxurXcVOcdWCExvdBm4G8TwrrbYCdD9D0Nx2Utaez5ExgwdzE_TbPvd4CiU-CM4kfJX3YUXIGBwEndtzKs5SeOvc5mWf2bXT0&prev=RQABBB60CA98458C&p=17&pg=39)

* Intellectual Capital Resources
* Amsterdam
* October 15

You will define block and system-*level* architectures and drive RTL implementation across multiple projects ... VerantwoordelijkhedenDefine FPGA architectures and system-*level* designs Oversee RTL development and timing ... Experience with PCIe, high-speed SerDes, networking, or memory interfaces Strong understanding of system-*level*

report problem

[### Business Development Director - Technology Consulting Services](/clickout/4714484db5ed4ac5?ql=q&sig=dbee9c714d13c07e4a0295a0593166bc96880bf5&e=5STz-HcUmZLL6SdTVPFcxvxTfUpVMSoycc3h_hZhg7UxV6eNYVP3x18QdXViTsUo98bxYjvkuBF0jIVYMzmpp40K4NNRj3ydfdecytHIfMd3TH5C_XLV7Z_GvzAKKNBCvnNJaxOcSEpheHbUFbigjYpIkHg24tYwvvNVwgkI5LFDnqGDP0ia_baUXbHyv16pHuezYtF3WY45IfUd5XiobVcIVZBxOTjH24dY41R9I6WMp1DCYirA5on_BwO-7ecgrsGf0mrps97hgR2sbdvZ8QSoxw01z4462LBHl3UaCLeMvbIXxTG3eDLaAZnlDlOn_EEiiF54Sw6R_vRvdAluHF9eNTgnk8XmN2QsaKtFQEqKAAKgr2n6_cZU6cLAqTFfj9naT1QxkIJh2ke5D0yECqAQ5oIkSx28XpeKmURaO4xucOSHdChN7M1g_0hwLSSCuaNlDfN5a3qSyVKI4Cdb5CmAqkzEOJzdB0p7uU7gZIpvaJDcxxhgK16XDmBi3jeUN3G1ZqPLIogtJwJeBJhnPT0uI-DCRTEFRLT3QZ2fKh43tI8WP4hvCot31OjR927IynfSKOqj3sKwGr36-hoa0I2YNp0XoxNaZGhuqUOWa18r4pwCsAwNBwZYQKsiRlTQWkqJ01jxiKkyI28Le5No471KI7F74DRcYBXnzr5BeBDiRfKLOwJne16_vZD3D9kXITAgK0Pl98bt2ApkovfksauBkL2cp373joNdceHPAXhzjDAV5eatb8UrWKhf_PV633P2nmvPPR0bECVwSPligrnJ9IOWDszezahCMoIkawhigRML0gJxGkXAllA53kX1Q5mIu87UJkiOSDKTMzJ71q_d8KI-uW4Kw_MdriWJdCj7zX16PYxbDxAHPowdk1k_3KUKH_RRdtOxojd1yDXggb1oVDlt3CvoJjKdZX6-Bwm9WOI99EdxRCAGyyaRNsTrytZhZ0M0F8mGuBSfZ3sZ7LSA7JWm3DkKrItJYNuQKTpuSekeePYRCsgQZKZwyk-f_Z1G6z5vnvrL5M-PW3FxZ4ePaxqzF9n3V7oDXU_OlIThJ0YTVPk-Y508B_W3zIsCcR0FQvSO8XJT4cgd3qo1DRbY3LxV19dfN3O5xpiPQ11Kn2X3b71m8wePiuro50Ex8h_EQl_EX-tLLe42ftOf3TDMTK8hwVoi11w6PEnjgG96-mCk1zGihrau8dnRq921bSTpR9aaB5cAlxRzeuvWcYmADL7PvdOJUcDkkbsZAWPuNlk0bcu7vVX1egXbQvarLI1G_qXO9PkZBjd_LuYO0jfLV-dR4qDM-8CWFWGfFHXjCGMvsPeC-KMpFqvf-DFR2kx-95Se7MwVic2kboXxGQuxOuhdeDmbm-l_BpkmzuGrSjFtQb3RO7A7vfot2sAwxRcgvuTSSiD9S47BTfBa0p11mxwSJ7ELulS3uiM4fajR8-TvNIuL3iOEtP-z&prev=RQABBB60CA98458C&p=18&pg=39)

* Spectral Industries
* Delft
* October 13

For Spectral Industries, we are seeking a senior-*level* Business Development professional whose primary ... To support this market, Spectral Industries is also recruiting a medior-*level* Business Development professional

report problem

[### Senior Director of Business Development, Technology](/clickout/065fd71e6b0df679?ql=q&sig=a0ee05b61d422fe2e24d54fc6ec94a4e6ee53607&e=MK-K-EegXEIrYDFUeVZtbtplX73hY-mjMqWITi24yXdauM4tN7xgZJCgzgkU38JuZLBmclzjDyQKB3SR_7sCGayiC8w0P599dlcHX4KvZJFOJfkO6VryHAJvWX4PtKb5Av2LiBngi9LSNFS5VIuEgqqz-6FRtgmng5JEeDrayXDA2hDNsykHodtsI1JHrujHGzGdwi7fAlS5Np2pCQwb6rfI4hoWl2F2k7QhM-P8wJDNt19hcd47kgNJEC3UKGXBY6r8zhDW7_VQRNkYdWR374hX60q0hALvNthW92wzeZdp_wr0_1CYRj-3nP8QgRQzWQTN6jvGbNgntR1IA_MLiPYcLxWqZ74aohm8Eepgxl0igtoUo-LSO5PMn72BohStH_N9UHXZ6-9gpE_QAlu-BmrtZC4JaxCgLrpY0aL4Ki3inGskgEYjzPygxzNY4rHMfTipz8N8GvZEXsheYT2TyIYPddhtHLfZRXzJKKTDzXEV7CRKp6Gs9enTYjDa4GhKeotFr-JKStcO_WS0STqovICB0F-S47GcISJneM03hhuelV8i1GozxYtSuMUCYRFFahQAsQSuSJY65uK50w1-vS93xYJ_iziNjrEnC0ZEVP6ArYrdHnBI99rG9QqMPtnPJwdsq9RbEBRBzFPrc8TZGdByO7W39NMSyPH1zzPVDjcMpfJGnp4PDDZdLw2C5yQlz3bqfDRmwJOI8ajMd-8QfW6ZCg2uEGgY3RqMMoWMHkrIEXboOd-cvZAVwB2o6GqXkYK3ZI1zkC-ySXol7qQa0K9sy1iy_Hjp0kJ9a_B0PLh-dNCbtXnhsyqMOXS7Q23PGhjBQMGuPZQj6VIt37UMYt0E3os92spdkYrrJGjuhFSN3Jz1o5GetLBj5MjN8lqZIjZ3qV_jUroIgEQiRZCRyduX38nDsyVL20fVBjyxscK6T0IgEQ_Z01bjOAY5GAbrrEgqR7QeUiF7yqDCbRfb5ytOSBnrQnwwBrjgyfXeT3ZWJ_4381gZPWEmYBUsAnpmGLx9sA8kQn3kbX8En1SYDK3k5np7P_DpbfGzVjzG3YvSYY4ptcnFEbNAa7yLPSiDbZTwDKfpXzIo6dbNyf_I0zLXW9z3nTAM_5Hg7zveUfkBjNl0Z66MheP0qtH1UYmntQVpo2XPUfKDoJwp9YQf8HhSCc8Pi-cltW9B7QgXRFxHXq-DyAx0gKqjX4fXhSAOPFpqNnboQF-JgOr42JSawjmBhUzpsWRw2duNCLJXxZuRuEYIq26_1FS4pL-l1lo32GVQu-KLOxWkSijPfRxL25fNmlW2Qp5_X4jUrBEtscndNEZV5MPZpBDS394_lfe5cLNW2elxNYqQcTBAG8GWgNISxTHUU-t2771iTjt2XBcgsn8-NjbP898jb09tVhV0xwvU4s8KidrT1NBDuHvxy5JjIQnHdzIiBOQ_V40XtMniEoVNbA&prev=RQABBB60CA98458C&p=19&pg=39)

* Spectral Industries
* Delft
* October 13

For Spectral Industries, we are seeking a senior-*level* Business Development professional whose primary ... To support this market, Spectral Industries is also recruiting a medior-*level* Business Development professional

report problem

[### Business Development Director - Tech Consultancy](/clickout/c44e14de6acdc33e?ql=q&sig=4345ed76d8f9da504b19ec697ad81ed12dd441e3&e=lVRLK57Gi3sYswZSQY7xi2BawQowa5WF5PX-Qeh2AUZHTvMh6VI2Avo0Qy0wEBg1XbVnKgOro8a0TkGBUhjdeSpDq54Sy6xZGDYvfEYv2XqapYUzMqYakvOk_PKVAQR1zP0eliMm2KsmG-9YH12GMjkZg3cgLTiamjTNa46mj-zX0mD7ITC4mIONzh1IQwMkEQxqHm5S8nu00mriO8FdDjNjwtakmsRp07zDaYfyILxPtF5OKA78XsiyHsYGtoxHKQdGcsvz-NdvTpDSMbew8KxN79R4WVbdxcHeMdsF5Epyx1nWx2PBOH2UpEw1jJjRk_nrT1uuyObpBG9bmIbjz3FnNmy1UbPdbvVWGVqKq4kIpGRmYEuemKyc_vU5zuybtaFH0L9O0okXBV-cbcKdKUvGVeAMrLrL7KhuaW-LiHXmiANG-tMvvHbyEMAUwmZxkvbY7zwqVJupZK5vyhYiy7JqH87SmUV9u93L-Um2RvoWgdrW_7pzISQy7X5msquoRs-Wa1SyvLOkyLyVFzsUN0ebNe3AdZwL4hM8SPygZ4Rfr0w3SDj96BCxIkfxuW1xnQPHJ5j6xHrCX6X-wInJbckyNQEOAW8GM2hsC52eDhLgBcZMN9wIhWT1bEPxewRrTX5oQITiErHDtRb3-O3AKs6geI2jRqFTZva7hUQ2uXz_Mw1I-_1an7_MAIusAsdXviYyN_3S1xWBiBZOPxahPQ24EdZX1oPBNl_otaepjWfoZCdQZGDk7E2G3ceNbxmY1Y0QkEDsmvo5KTLKqQ_makrNFWpnjBzAmdyxkgmKNVdRn471jAf9P_Exdi0FFutAW5RSSCrn7PLPx2ZTlc061qxOcqJIBUO4GD1eOCjxrOfHrAFcz7rw9-OubWG_vpBcCJznFNUxK1wP2ype1sJIP9oSLbPCQneQ1RZ7fDgLAybZkbhPKYZs0bOHphs7W56JXprpuCJm997KZA2ceAEnnD4R8y5kw-wooKEa3hL92Xjleiy7cZCWo8DJXgfHA1gEKpwzcFwHU45LG2tUdJAh4CzC5t4jr0x8xXN9lLTkQLLjCdlxwHQqkU3zsFHwge2VFsvDX_U8ToEZJ1lYOltlFaM3sQIbXOBZyy3xhAB-b-f52Ul-KKAluRuvwYbTdGNkTk_Q3Q1QsusZAQnrwXvxr6fx8AoWlo4lX7BaB4LOR8nljMTEz3htxslZw7U6yNsfhZr04gLKFWLf55-RFfbee0rk-_pVgeZX22YPY90O5EPkVAQKDmQIDMLpC1F_bGlkoZLY3JH-QYZ4clrxxEE-6V_ostautAyiKswtzWmf0d9cjnCjqnJMmun3ZGCsh41mkKhLWc_WN7LfTSe6KYnbAaJg4faxLKT19izzBYrOAfznCNBsSWP0IZT7KvA_Z-06X0cmv5KtDGF5xgBf3MBJBdxGwmb2stzHTDqAM5X4DoM&prev=RQABBB60CA98458C&p=20&pg=39)

* Spectral Industries
* Delft
* October 13

For Spectral Industries, we are seeking a senior-*level* Business Development professional whose primary ... To support this market, Spectral Industries is also recruiting a medior-*level* Business Development professional

report problem

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#### entry level in Cities...

* 2063

  ![Amsterdam](/public/img/coa/nl.amsterdam.png "Coat of arms of Amsterdam")

  [Amsterdam](/in/amsterdam/entry_level "English jobs in Amsterdam")
* 243

  ![Rotterdam](/public/img/coa/nl.rotterdam.png "Coat of arms of Rotterdam")

  [Rotterdam](/in/rotterdam/entry_level "English jobs in Rotterdam")
* 241

  ![Eindhoven](/public/img/coa/nl.eindhoven.png "Coat of arms of Eindhoven")

  [Eindhoven](/in/eindhoven/entry_level "English jobs in Eindhoven")
* 207

  ![Utrecht](/public/img/coa/nl.utrecht.png "Coat of arms of Utrecht")

  [Utrecht](/in/utrecht/entry_level "English jobs in Utrecht")
* 162

  ![The Hague](/public/img/coa/nl.s-gravenhage.png "Coat of arms of The Hague")

  [The Hague](/in/s-gravenhage/entry_level "English jobs in The Hague")
* 87

  ![Breda](/public/img/coa/nl.breda.png "Coat of arms of Breda")

  [Breda](/in/breda/entry_level "English jobs in Breda")
* 87

  ![Delft](/public/img/coa/nl.delft.png "Coat of arms of Delft")

  [Delft](/in/delft/entry_level "English jobs in Delft")
* 78

  ![Venlo](/public/img/coa/nl.venlo.png "Coat of arms of Venlo")

  [Venlo](/in/venlo/entry_level "English jobs in Venlo")
* 73

  ![Tilburg](/public/img/coa/nl.tilburg.png "Coat of arms of Tilburg")

  [Tilburg](/in/tilburg/entry_level "English jobs in Tilburg")
* 62

  ![Lelystad](/public/img/coa/nl.lelystad.png "Coat of arms of Lelystad")

  [Lelystad](/in/lelystad/entry_level "English jobs in Lelystad")
* 57

  ![s-Hertogenbosch](/public/img/coa/nl.s-hertogenbosch.png "Coat of arms of s-Hertogenbosch")

  [s-Hertogenbosch](/in/s-hertogenbosch/entry_level "English jobs in s-Hertogenbosch")
* 54

  ![Haarlem](/public/img/coa/nl.haarlem.png "Coat of arms of Haarlem")

  [Haarlem](/in/haarlem/entry_level "English jobs in Haarlem")
* 47

  ![Maastricht](/public/img/coa/nl.maastricht.png "Coat of arms of Maastricht")

  [Maastricht](/in/maastricht/entry_level "English jobs in Maastricht")
* 45

  ![Almere](/public/img/coa/nl.almere.png "Coat of arms of Almere")

  [Almere](/in/almere/entry_level "English jobs in Almere")
* 40

  ![Apeldoorn](/public/img/coa/nl.apeldoorn.png "Coat of arms of Apeldoorn")

  [Apeldoorn](/in/apeldoorn/entry_level "English jobs in Apeldoorn")
* 39

  ![Ede](/public/img/coa/nl.ede.png "Coat of arms of Ede")

  [Ede](/in/ede/entry_level "English jobs in Ede")
* 37

  ![Roosendaal](/public/img/coa/nl.roosendaal.png "Coat of arms of Roosendaal")

  [Roosendaal](/in/roosendaal/entry_level "English jobs in Roosendaal")
* 37

  ![Zwolle](/public/img/coa/nl.zwolle.png "Coat of arms of Zwolle")

  [Zwolle](/in/zwolle/entry_level "English jobs in Zwolle")
* 36

  ![Bergen op Zoom](/public/img/coa/nl.bergen-op-zoom.png "Coat of arms of Bergen op Zoom")

  [Bergen op Zoom](/in/bergen-op-zoom/entry_level "English jobs in Bergen op Zoom")
* 33

  ![Deventer](/public/img/coa/nl.deventer.png "Coat of arms of Deventer")

  [Deventer](/in/deventer/entry_level "English jobs in Deventer")
* 33

  ![Heerenveen](/public/img/coa/nl.heerenveen.png "Coat of arms of Heerenveen")

  [Heerenveen](/in/heerenveen/entry_level "English jobs in Heerenveen")
* 31

  ![Leeuwarden](/public/img/coa/nl.leeuwarden.png "Coat of arms of Leeuwarden")

  [Leeuwarden](/in/leeuwarden/entry_level "English jobs in Leeuwarden")
* 28

  ![Harderwijk](/public/img/coa/nl.harderwijk.png "Coat of arms of Harderwijk")

  [Harderwijk](/in/harderwijk/entry_level "English jobs in Harderwijk")
* 28

  ![Tiel](/public/img/coa/nl.tiel.png "Coat of arms of Tiel")

  [Tiel](/in/tiel/entry_level "English jobs in Tiel")
* 24

  ![Hoogeveen](/public/img/coa/nl.hoogeveen.png "Coat of arms of Hoogeveen")

  [Hoogeveen](/in/hoogeveen/entry_level "English jobs in Hoogeveen")
* 23

  ![Zaandam](/public/img/coa/nl.zaanstad.png "Coat of arms of Zaandam")

  [Zaandam](/in/zaanstad/entry_level "English jobs in Zaandam")
* 21

  ![Sittard](/public/img/coa/nl.sittard-geleen.png "Coat of arms of Sittard")

  [Sittard](/in/sittard-geleen/entry_level "English jobs in Sittard")
* 19

  ![Wageningen](/public/img/coa/nl.wageningen.png "Coat of arms of Wageningen")

  [Wageningen](/in/wageningen/entry_level "English jobs in Wageningen")
* 15

  ![Echt](/public/img/coa/nl.echt-susteren.png "Coat of arms of Echt")

  [Echt](/in/echt-susteren/entry_level "English jobs in Echt")
* 12

  ![Groningen](/public/img/coa/nl.groningen.png "Coat of arms of Groningen")

  [Groningen](/in/groningen/entry_level "English jobs in Groningen")
* 9

  ![Ridderkerk](/public/img/coa/nl.ridderkerk.png "Coat of arms of Ridderkerk")

  [Ridderkerk](/in/ridderkerk/entry_level "English jobs in Ridderkerk")
* 6

  ![Roermond](/public/img/coa/nl.roermond.png "Coat of arms of Roermond")

  [Roermond](/in/roermond/entry_level "English jobs in Roermond")
* 5

  ![Moerdijk - Zevenbergen](/public/img/coa/nl.moerdijk.png "Coat of arms of Moerdijk - Zevenbergen")

  [Moerdijk - Zevenbergen](/in/moerdijk/entry_level "English jobs in Moerdijk - Zevenbergen")
* 4

  ![Emmen](/public/img/coa/nl.emmen.png "Coat of arms of Emmen")

  [Emmen](/in/emmen/entry_level "English jobs in Emmen")
* 4

  ![Sliedrecht](/public/img/coa/nl.sliedrecht.png "Coat of arms of Sliedrecht")

  [Sliedrecht](/in/sliedrecht/entry_level "English jobs in Sliedrecht")
* 4

  ![Zaltbommel](/public/img/coa/nl.zaltbommel.png "Coat of arms of Zaltbommel")

  [Zaltbommel](/in/zaltbommel/entry_level "English jobs in Zaltbommel")
* 3

  ![Edam](/public/img/coa/nl.edam-volendam.png "Coat of arms of Edam")

  [Edam](/in/edam-volendam/entry_level "English jobs in Edam")
* 3

  ![Middelburg](/public/img/coa/nl.middelburg.png "Coat of arms of Middelburg")

  [Middelburg](/in/middelburg/entry_level "English jobs in Middelburg")
* 3

  ![Terneuzen](/public/img/coa/nl.terneuzen.png "Coat of arms of Terneuzen")

  [Terneuzen](/in/terneuzen/entry_level "English jobs in Terneuzen")
* 2

  ![Hardenberg](/public/img/coa/nl.hardenberg.png "Coat of arms of Hardenberg")

  [Hardenberg](/in/hardenberg/entry_level "English jobs in Hardenberg")
* 2

  ![Kampen](/public/img/coa/nl.kampen.png "Coat of arms of Kampen")

  [Kampen](/in/kampen/entry_level "English jobs in Kampen")
* 2

  ![Langedijk](/public/img/coa/nl.langedijk.png "Coat of arms of Langedijk")

  [Langedijk](/in/langedijk/entry_level "English jobs in Langedijk")
* 2

  ![Leidschendam](/public/img/coa/nl.leidschendam-voorburg.png "Coat of arms of Leidschendam")

  [Leidschendam](/in/leidschendam-voorburg/entry_level "English jobs in Leidschendam")
* 2

  ![Naarden](/public/img/coa/nl.naarden.png "Coat of arms of Naarden")

  [Naarden](/in/naarden/entry_level "English jobs in Naarden")
* 2

  ![Schouwen-Duiveland](/public/img/coa/nl.schouwen-duiveland.png "Coat of arms of Schouwen-Duiveland")

  [Schouwen-Duiveland](/in/schouwen-duiveland/entry_level "English jobs in Schouwen-Duiveland")
* 1

  ![Bussum](/public/img/coa/nl.bussum.png "Coat of arms of Bussum")

  [Bussum](/in/bussum/entry_level "English jobs in Bussum")
* 1

  ![Goes](/public/img/coa/nl.goes.png "Coat of arms of Goes")

  [Goes](/in/goes/entry_level "English jobs in Goes")
* 1

  ![Hof van Twente](/public/img/coa/nl.hof-van-twente.png "Coat of arms of Hof van Twente")

  [Hof van Twente](/in/hof-van-twente/entry_level "English jobs in Hof van Twente")
* 1

  ![Lichtenvoorde](/public/img/coa/nl.lichtenvoorde.png "Coat of arms of Lichtenvoorde")

  [Lichtenvoorde](/in/lichtenvoorde/entry_level "English jobs in Lichtenvoorde")
* 1

  ![Oud-Beijerland](/public/img/coa/nl.oud-beijerland.png "Coat of arms of Oud-Beijerland")

  [Oud-Beijerland](/in/oud-beijerland/entry_level "English jobs in Oud-Beijerland")
* 1

  ![s-Gravenzande](/public/img/coa/nl.s-gravenzande.png "Coat of arms of s-Gravenzande")

  [s-Gravenzande](/in/s-gravenzande/entry_level "English jobs in s-Gravenzande")
* 1

  ![Winschoten](/public/img/coa/nl.winschoten.png "Coat of arms of Winschoten")

  [Winschoten](/in/winschoten/entry_level "English jobs in Winschoten")
* 1

  ![Zwartewaterland](/public/img/coa/nl.zwartewaterland.png "Coat of arms of Zwartewaterland")

  [Zwartewaterland](/in/zwartewaterland/entry_level "English jobs in Zwartewaterland")

#### entry level in Provinces...

* 2441

  ![North Holland](/public/img/coa/nl.noord-holland.png "Coat of arms of North Holland")

  [North Holland](/in/noord-holland/entry_level "English jobs in North Holland")
* 974

  ![South Holland](/public/img/coa/nl.zuid-holland.png "Coat of arms of South Holland")

  [South Holland](/in/zuid-holland/entry_level "English jobs in South Holland")
* 779

  ![North Brabant](/public/img/coa/nl.noord-brabant.png "Coat of arms of North Brabant")

  [North Brabant](/in/noord-brabant/entry_level "English jobs in North Brabant")
* 369

  ![Utrecht (province)](/public/img/coa/nl.utrecht-province.png "Coat of arms of Utrecht (province)")

  [Utrecht (province)](/in/utrecht-province/entry_level "English jobs in Utrecht (province)")
* 365

  ![Gelderland](/public/img/coa/nl.gelderland.png "Coat of arms of Gelderland")

  [Gelderland](/in/gelderland/entry_level "English jobs in Gelderland")
* 286

  ![Limburg](/public/img/coa/nl.limburg.png "Coat of arms of Limburg")

  [Limburg](/in/limburg/entry_level "English jobs in Limburg")
* 205

  ![Overijssel](/public/img/coa/nl.overijssel.png "Coat of arms of Overijssel")

  [Overijssel](/in/overijssel/entry_level "English jobs in Overijssel")
* 110

  ![Flevoland](/public/img/coa/nl.flevoland.png "Coat of arms of Flevoland")

  [Flevoland](/in/flevoland/entry_level "English jobs in Flevoland")
* 67

  ![Friesland](/public/img/coa/nl.friesland.png "Coat of arms of Friesland")

  [Friesland](/in/friesland/entry_level "English jobs in Friesland")
* 62

  ![Drenthe](/public/img/coa/nl.drenthe.png "Coat of arms of Drenthe")

  [Drenthe](/in/drenthe/entry_level "English jobs in Drenthe")
* 31

  ![Groningen (province)](/public/img/coa/nl.groningen-province.png "Coat of arms of Groningen (province)")

  [Groningen (province)](/in/groningen-province/entry_level "English jobs in Groningen (province)")
* 15

  ![Zeeland](/public/img/coa/nl.zeeland.png "Coat of arms of Zeeland")

  [Zeeland](/in/zeeland/entry_level "English jobs in Zeeland")

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