208 entry level English-speaking jobs in Delft

  • Fiducial
  • Delft
  • March 12
Additional information Seniority level: Entry level Employment type: Full‐time Job function: Engineering
  • Allseas
  • Delft
  • February 28
applications.Fulfilment of all training and qualification requirements in accordance with Allseas' Entry ... Level Matrix.Strong written and verbal communication, decisiveness, leadership, and problem analysis ... should have:Maritime engineering education and compliance with all STCW requirements.CoC with competency level ... dredging or offshore construction vessels.Experience in the engine room as Third Engineer is preferred.B1 level
  • OTT HydroMet
  • Delft
  • March 12
Seniority Level Entry level Employment Type Full-time Job Function Purchasing and Supply Chain Diversity ... Actively engages with the operation team and key partners, provides a high level of responsiveness and
  • Equal1
  • Delft
  • March 31
applications to low-level quantum processors control. ... Engineering to oversee and drive the architecture and development of our full software stack, from high level
  • IC Resources
  • Delft
  • March 12
You will lead top-level chip planning, deliver block-level layout, and support chip integration and tape-out ... level floorplanning, power distribution, shielding and device matchingLayout verification including ... DRC, LVS, and ERCChip-level integration and support for tape-outTraining and guidance for junior and ... helping to develop consistent layout methodologies and workflows across sites.Key responsibilities:Top-level ... and block-level layout for analog and digital blocksSchematic driven layout and constraint-based designChip
  • European Tech Recruit
  • Delft
  • March 15
chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard ... Layout Design Engineer you will lead top-level chip-planning and perform block-level custom layouts for ... Pass DRC, LVS, and ERCContribute to various chip-level routing and layout needsPerform chip level integration ... local and global design and layout teams in multiple design centres across different time zonesLead Top-level ... , signal integrity and power distribution problems while meeting area constraintsExperience in chip-level
  • Sharp Brains
  • Delft
  • March 31
OverviewSkill Set: Deskside support Technician Level 1 Designation: Backfill Day rate Contract: B2B/Freelance
  • Dawn Aerospace
  • Delft
  • March 3
the systems and customer project teams.This role combines hands-on electrical engineering with system-level ... Working at system level, you will bridge electronics design, testing/verification, and operations, collaborating ... You'll Do Own electronics requirements definition, verification planning, and execution of system-level ... electronic systems.2+ years of experience in electrical engineering, system integration, or system-level ... compatibility with mission requirements.Triage, troubleshoot and repair electrical hardware issues at system-level
  • The Preferred Supplier
  • Delft
  • March 12
Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS ... Responsibilities Lead Top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS ... Pass DRC, LVS, and ERC Contribute to various chip-level routing and layout needs Support other projects ... , signal integrity and powerdistribution problems while meeting area constraints Experience in chip‐level ... constraints Design die-area efficient layouts according to circuit designer requirements Perform block or top-level
  • Tective Robotics
  • Delft
  • March 7
We are looking for a Junior/Mid-Level Frontend Developer (TypeScript) to help us build the interfaces ... systems in a growing deep-tech companyGrow from a strong front-end foundation toward broader system-level
  • Qualinx B.V.
  • Delft
  • January 25
requirements to block-level specifications; participate in system-level modelling and simulation activities ... Design and develop system architecture for ultra-low-power analog applications; translate system-level ... Responsibilities Perform detailed transistor-level circuit design, including design capture, simulation ... Design Engineer, you will be responsible for the design, implementation, and validation of transistor-level
  • Delft University of Technology
  • Delft
  • March 20
Your work will include system-level modeling, architectural exploration, transistor-level circuit design
  • Rotterdam Innovation City
  • Delft
  • February 28
our microwave-to-optics conversion technology and its application to quantum computing to the next level
  • Meatable
  • Delft
  • March 13
, and industry stakeholders.Monitor global regulatory trends and provide strategic advice on market entry
  • Qualinx
  • Delft
  • March 12
Job DescriptionThe Qualinx Hardware and Software System Level Integration and Validation Engineering ... Embedded systems: Strong understanding of embedded systems, including hardware and low‐level software ... The HW&SW System Level I&V essential skills include a strong understanding of embedded and communication ... The HW&SW System Level Integration & Validation engineering's key responsibilities include the definition ... validation, with some roles requiring +10 years' experience for Senior/Lead role, 4-6 years for Mid level
  • Online Payment Platform
  • Delft
  • February 2
we bring in new talent to meet the demands of our expanding enterprise.Your track record showsSenior level
  • TOPdesk
  • Delft
  • March 18
Translate board‐level priorities into structured, trackable programs with clear KPIs and financial impact
  • Qabird
  • Delft
  • March 11
You will own the complete IC design flow including block‐level specification, topology selection, component
  • Lobster Robotics
  • Delft
  • March 12
You will own the complete IC design flow including block‐level specification, topology selection, component
  • ElectroChemical Flow Systems laboratory
  • Delft
  • March 20
apply your technical knowledge to projects with key companies in the biotech industry at a doctorate level
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