102 entry level English-speaking jobs in Delft

Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS ... Responsibilities Lead Top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS ... Pass DRC, LVS, and ERC Contribute to various chip-level routing and layout needs Support other projects ... , signal integrity and powerdistribution problems while meeting area constraints Experience in chip‐level ... constraints Design die-area efficient layouts according to circuit designer requirements Perform block or top-level

Driving system-level performance improvements through cross-functional collaboration, test automation

Location: Delft, Netherlands / Hybrid Sector: Quantum Computing, Scientific Hardware & Advanced Computing Level

accuracy over time and embed best practices (coverage ratios, commit vs. best case discipline, stage entry

We are seeking a Senior Systems Architect to lead the system-level design frameworks and tooling that

Our ground segment covers everything from user interfaces for commanding and telemetry to low-level processing

You help tackle low-level security issues and build tools that prevent insecure software patterns. ... tooling and playbooks that make secure software the default, translating findings into concrete low-level

Requirements You have at least 10 years of experience in embedded/low level software development . ... You create unit tests, perform system-level testing, and support hardware-in-the-loop setups to verify ... You have experience with spacecraft flight software , or comparable vehicle software requiring a high level

Application materials (combine PDFs and submit in CV entry): Motivation letter that includes a description

These low-level, shallow, horizontally extensive clouds cover one-fifth of the Earth’s surface.

The energy transition is transforming the way distribution systems at the low-voltage (LV) level are ... heat pumps, complemented by smart buildings, will unlock the required energy flexibility at the LV level

to macro-level transition dynamics. ... The focus is on developing a multi-level ABM that links micro-level consumer and organisational decisions ... inverse generative methods, the candidate will uncover which individual behaviours drive observed system-level

Good communication Working knowledge of either Xilinx Vivado or Intel FPGA Quartus VHDL Module-level ... vendor (FPGA, third party ASICs/software) documentation Write self‑checking testbenches at the module level ... Imagine what it takes to talk to 1000 qubits, with nanosecond‑level synchronization and all‑to‑all connectivity

Seniority level Mid‐Senior level Employment type Full‐time Job function Engineering, Manufacturing, and

Good communication Working knowledge of either Xilinx Vivado or Intel FPGA Quartus VHDL Module-level ... vendor (FPGA, third party ASICs/software) documentation Write self-checking testbenches at the module level ... Imagine what it takes to talk to 1000 qubits, with nanosecond-level synchronization and all-to-all connectivity

specifications Perform block level RTL design and verification using industry leading EDA tools Support ... following: Digital architecture development and technical feasibility studies Writing detailed block-level ... design for optimal performance, area and power constraints trade- offs Document detailed block and top -level

Seniority level Not Applicable Employment type Full‐time Job function Engineering and Information Technology ... optimize quantum control workflows tailored to customer applications Troubleshoot complex software, system‐level

This field is rapidly growing and will impact society on a global level. ... You will build system-level models, simulators, and a robust C++ reference model stack that acts as the ... Model Systems & Protocols: Develop system-level behavioral models of data paths (DAC/ADC signal chains ... directly define what "correct behavior" means for teams developing and verifying RTL, firmware, and system-level

Working on SoC‐level validation and bring‐up, managing tests from component‐level through to full system

maintain the verification matrix and overall test architecture across component, subsystem, and system level ... Translate system‐level requirements into an end‐to‐end verification strategy, determining whether requirements ... performance, stability, interfaces, fault handling, and functional behaviour at board, subsystem, and system level