227 entry level English-speaking jobs in Delft

Job Title: Junior Spatial Perception & Multi-Sensor Fusion Engineer (PhD/MSc Entry Level) Location: Netherlands ... distributed sensing networks Support hardware bring-up, integration, and field testing Debug complex system-level ... Understanding of embedded or constrained compute environments Ability to independently debug complex system-level

Additional information Seniority level: Entry level Employment type: Full‐time Job function: Engineering

applications.Fulfilment of all training and qualification requirements in accordance with Allseas' Entry ... Level Matrix.Strong written and verbal communication, decisiveness, leadership, and problem analysis ... should have:Maritime engineering education and compliance with all STCW requirements.CoC with competency level ... dredging or offshore construction vessels.Experience in the engine room as Third Engineer is preferred.B1 level

You will lead top-level chip planning, deliver block-level layout, and support chip integration and tape-out ... level floorplanning, power distribution, shielding and device matchingLayout verification including ... DRC, LVS, and ERCChip-level integration and support for tape-outTraining and guidance for junior and ... helping to develop consistent layout methodologies and workflows across sites.Key responsibilities:Top-level ... and block-level layout for analog and digital blocksSchematic driven layout and constraint-based designChip

Seniority Level Entry level Employment Type Full-time Job Function Purchasing and Supply Chain Diversity ... Actively engages with the operation team and key partners, provides a high level of responsiveness and

Seniority level Entry level Employment type Full‐time Job function Information Technology Industries:

the systems and customer project teams.This role combines hands-on electrical engineering with system-level ... Working at system level, you will bridge electronics design, testing/verification, and operations, collaborating ... You'll Do Own electronics requirements definition, verification planning, and execution of system-level ... electronic systems.2+ years of experience in electrical engineering, system integration, or system-level ... compatibility with mission requirements.Triage, troubleshoot and repair electrical hardware issues at system-level

calculations, designand verification simulations to ensure building blocks meet specificationsat the schematic level

Chain of Space Innovation – Technical Buyer at Axient Systems Location: Axient Systems office – Delft Level

Beyond your technical expertise, you will act as a mentor and guide for junior- and mid-level engineers

What you will own: System-Level RF Architecture: Shaping signal paths from AWG to QPU, ensuring phase ... Acting as the primary technical interface for global suppliers, ensuring their hardware meets our QPU-level

our microwave-to-optics conversion technology and its application to quantum computing to the next level

our microwave-to-optics conversion technology and its application to quantum computing to the next level

requirements to block-level specifications; participate in system-level modelling and simulation activities ... Design and develop system architecture for ultra-low-power analog applications; translate system-level ... Responsibilities Perform detailed transistor-level circuit design, including design capture, simulation ... Design Engineer, you will be responsible for the design, implementation, and validation of transistor-level

Programmer at Triumph Studios, you will be instrumental in taking our proprietary Creator engine to the next level

Follows standard practices and procedures • Normally receives detailed instructions on all work • Typical entry

The long-term goal of our research is to understand synapse assembly and disassembly at the molecular level ... develop and apply advanced computational methods to visualize cellular structures at the molecular level

we bring in new talent to meet the demands of our expanding enterprise.Your track record showsSenior level

You will be responsible for the verification of our digital IP blocks and the simulation of chip‐level ... SoC.As a Digital ASIC Verification engineer you will develop test benches and test cases for block‐level ... performance bugs.You are responsible for the verification of various IPs/Sub IPs integrated to the top level ... simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level

You should be comfortable pitching to C-level executives. Commitment: Join me in the 10-week YES!