195 English-speaking jobs in Delft

Design the control stack architecture for scaling quantum systems from 100+ to 1,000+ qubits. Requires 10+ years in software engineering across Python, C/C++, embedded systems, and FPGA understanding.

Lead Engineer for the Automation Team, driving technical ownership and engineering excellence. This role connects disciplines, mentors engineers, and helps define the long-term automation strategy.

Design and implement ServiceNow solutions within an agile IT application team. Translate business needs into technical outcomes, improving and integrating ServiceNow implementations. Requires 5+ years of ServiceNow experience with modules like ITSM, SAM, HAM, and SPM.

Senior Hardware Security Expert needed for hardware design reviews, vulnerability analysis, and test plan design. Requires expertise in secure elements, SoCs, embedded systems, and cryptographic algorithms.

Technical Sales Engineer to promote quantum technology. Responsibilities include customer contact, sales process involvement, and solution customization. Requires an MSc in physics/optics and excellent English skills.

Production Test Engineer to test, characterize, and validate SNSPD systems. Tasks include optical/electrical characterization, quality control, and troubleshooting. Requires a degree in Physics, Optics, or related field.

Senior Graphite Engineer to lead graphite engineering for a 25 MWe / 70 MWth HTGR. Responsibilities include defining specifications, assessing material behavior under irradiation, and co-designing reactor internals. Requires MSc/PhD and 10+ years of relevant experience.

Experimental Quantum Engineer - R&D operates and elevates cryogenic measurement infrastructure. Responsibilities include characterizing R&D prototypes, analyzing data, and developing Python-based automation for high-throughput device characterization.

Security Evaluator assesses software implementations across diverse products by defining advanced attack scenarios to uncover vulnerabilities. This role involves analyzing code, communicating findings to developers, and supporting certification efforts in mobile and embedded solutions.

Lead security evaluation projects as a Senior CC Evaluator for telecom, ICs, and smart cards. Act as a technical reference, mentor colleagues, and drive R&D to support business development. Requires a technical degree and proven CC project experience.

This 1-year internship focuses on AI-driven lead generation and EMEA market strategy for Device Security. Responsibilities include executing outreach campaigns, qualifying high-intent leads, and analyzing pipeline performance.

Support development and release of production test solutions for Qualinx products. Contribute to digital and memory test development, characterization, and yield improvement. Requires 5+ years in semiconductor test engineering.

Lead one or two technical teams (front-end, back-end, etc.) setting technical direction and owning delivery. Grow engineers into senior/staff roles while operating within an AI-native SDLC.

Senior Quantum R&D Engineer to develop next-gen QPU architectures. Focus on designing, validating, and iterating on-chip components like couplers and readout systems using superconducting quantum device expertise.

Senior Quantum Algorithm Expert to investigate and develop quantum applications solving real-world bottlenecks. Key tasks include mapping use cases, resource estimation, and leading automation for algorithm translation to physical QPU specifications. PhD required.

Senior System Architect to lead system-level design frameworks for QPU technology deployment across global HPC infrastructures. Own MBSE tool development, full-stack blueprints, and component libraries. Requires 8+ years in complex systems engineering.

Own end-to-end release coordination across FPGA, embedded software, and documentation. Define release-readiness criteria and make go/no-go decisions across all contributing teams. Requires technical grounding and strong stakeholder management.

Senior IC Layout Design Engineer needed for analog and full custom digital layout in CMOS/BiCMOS. Responsibilities include top-level planning, block layout, and tape-out support. Requires 6-12 years' experience and proficiency in Cadence Virtuoso.

Evaluate payment terminal and secure hardware for PCI PTS compliance. Responsibilities include hardware penetration testing, tamper-resistance evaluation, and logical security testing of embedded systems. Requires technical background in hardware/embedded security.

Senior SoC Architect defines high-level SoC architecture, guides physical design, and ensures software support. Requires 12+ years in RTL/Architecture, deep knowledge of ARM MCUs, and ASIC flows.